TMP86xy12MG Toshiba, TMP86xy12MG Datasheet - Page 58

• Manufacturer Part Number: TMP86xy12MG
• Manufacturer: Toshiba

Specifications of TMP86xy12MG

• Package: SSOP30
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 16
• Ram Size: 512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: IGBT
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 24
• Power Supply (v): 4.5 to 5.5

5. I/O Ports
input data should be externally held until the input data is read from outside or reading should be performed several
timer before processing. Figure 5-1 shows input/output timing examples.
timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro-
gram.
port.
The TMP86CH12MG has 4 parallel input/output ports (24 pins) as follows.
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external
External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This
Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O
Note: The positions of the read and write cycles may vary, depending on the instruction.
Port P0
Port P1
Port P2
Port P3
Instruction execution cycle
Instruction execution cycle
8-bit I/O port
5-bit I/O port
3-bit I/O port
8-bit I/O port
Primary Function
Output strobe
Input strobe
Data output
Figure 5-1 Input/Output Timing (Example)
Data input
External interrupt and timer counter input/output.
External interrupt, analog input and STOP mode release signal input.
External interrupt, serial interface input/output, UART input/output and timer
counter input/output.
Low-frequency resonator connections, external interrupt input, STOP mode
release signal input.
S0
S0
Fetch cycle
Fetch cycle
S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
Example: LD A, (x)
Example: LD (x), A
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Old
(b) Output timing
Fetch cycle
Fetch cycle
Secondary Functions
(a) Input timing
Read cycle
Write cycle
New
TMP86CH12MG