SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 237

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

B.4
B.4.1
B.4.2
B.4.3
ARM DDI 0165B
ARM9E-S design considerations
Master clock
JTAG interface timing
Interrupt timing
When an ARM9TDMI hard macrocell design is being converted to ARM9E-S, the
following areas require special consideration:
•
•
•
•
•
The master clock to the ARM9E-S, CLK, is inverted with respect to GCLK used on
the ARM9TDMI hard macrocell. The rising edge of the clock is the active edge of the
clock, on which all inputs are sampled.
All outputs are generated safely from the rising edge of CLK, with the following
exceptions:
CORECLKENOUT
DBGTDO
All JTAG signals on the ARM9E-S are synchronous to the master clock input, CLK.
When an external TCK is used, use an external synchronizer to the ARM9E-S.
As with all ARM9E-S signals, the interrupt signals, nIRQ and nFIQ, are sampled on
the rising edge of CLK.
When you are converting an ARM9TDMI hard macrocell design where the ISYNC
signal is asserted LOW, add a synchronizer to the design to synchronize the interrupt
signals before they are applied to the ARM9E-S.
Master clock
JTAG interface timing
Interrupt timing
Address class signal timing on page B-8
Data Aborts on page B-8.
Copyright © 2000 ARM Limited. All rights reserved.
This signal can change from the rising edge of CLK and has a
causal relationship with CLKEN.
This signal can change from the rising edge of CLK and has a
causal relationship with DBGSDOUT.
Differences Between the ARM9E-S and the ARM9TDMI
B-7