SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 133
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 133 of 290
- Download datasheet (5Mb)
6.9
ARM DDI 0165B
Busy-waiting and interrupts
ARM processor pipeline
LATECANCEL
Coprocessor pipeline
INSTR[31:0]
CHSD[1:0]
CHSE[1:0]
InMREQ
PASS
CLK
The coprocessor is permitted to stall, or busy-wait, the processor during the execution
of a coprocessor instruction if, for example, it is still busy with an earlier coprocessor
instruction. To do so, the coprocessor associated with the Decode stage instruction
drives WAIT onto CHSD[1:0]. When the instruction concerned enters the Execute
stage of the pipeline the coprocessor can drive WAIT onto CHSE[1:0] for as many
cycles as necessary to keep the instruction in the busy-wait loop.
For interrupt latency reasons, the coprocessor can be interrupted while busy-waiting,
causing the instruction to be abandoned. Abandoning execution is done through PASS.
The coprocessor must monitor the state of PASS during every busy-wait cycle. If it is
HIGH, the instruction must still be executed. If it is LOW, the instruction must be
abandoned. Figure 6-9 shows a busy-waited coprocessor instruction being abandoned
due to an interrupt.
Instr
Copyright © 2000 ARM Limited. All rights reserved.
Execute
Decode
WAIT
Execute
Execute
(WAIT)
(WAIT)
WAIT
Execute
Execute
(WAIT)
(WAIT)
Figure 6-9 ARM9E-S busy waiting and interrupts
WAIT
Execute
Execute
(WAIT)
(WAIT)
Ignored
Interrupted
Execute
Execute
(WAIT)
ARM9E-S Coprocessor Interface
Ignored
Exception
Aban-
doned
Entry
6-17
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