SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 106
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SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 106 of 290
- Download datasheet (5Mb)
Memory Interface
4.11
4.11.1
4.11.2
4-30
Endian effects for data transfers
Writes
Reads
The ARM9E-S supports 32-bit, 16-bit, and 8-bit data memory access sizes. The endian
configuration of the processor, set by CFGBIGEND, affects only nonword transfers
(16-bit and 8-bit transfers).
For data writes by the processor, the write data is duplicated on the data bus. So for a
16-bit data store, one copy of the data appears on the upper half of the write data bus,
WDATA[31:16], and the same data appears on the lower half, WDATA[15:0]. For
8-bit writes four copies are output, one on each byte lane:
•
•
•
•
This considerably eases the memory control logic design and helps overcome any
endian effects.
For data reads, the processor reads a specific part of the read data bus. This is
determined by:
•
•
•
Table 4-13 on page 4-22 shows which bits of the data bus are read for 16-bit reads, and
Table 4-14 on page 4-22 shows which bits are read for 8-bit transfers.
For simplicity of design, 32-bits of data can be read from memory and the processor
ignores any unwanted bits.
WDATA[31:24]
WDATA[23:16]
WDATA[15:8]
WDATA[7:0].
the endian configuration
the size of the transfer
bits 1 and 0 of the data address bus.
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0165B
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