SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 190

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Times
8.15
8-30
Store multiple registers
Store multiple (
instructions.
1.
2.
When a Data Abort occurs, the instruction continues to completion. The ARM9E-S
restores the modified base pointer (which the load activity before the abort occurred
might have overwritten).
The
Cycle
1 register
n registers
(n > 1)
STM
During the first cycle, the ARM9E-S calculates the address of the first word to be
transferred, while performing an instruction prefetch and also calculating the new
value for the base register.
During the second and subsequent cycles, ARM9E-S stores the data requested in
the previous cycle and calculates the address of the next word to be transferred.
Copyright © 2000 ARM Limited. All rights reserved.
cycle timings are shown in Table 8-24.
1
2
1
2
.
n
STM
IA
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
) instructions proceed in a similar fashion as load multiple
InMREQ,
ISEQ
I cycle
S cycle
I cycle
I cycle
I cycle
S cycle
INSTR
(pc+2i)
-
(pc+3i)
(pc+2i)
-
-
-
(pc+3i)
DA
da
-
da
da++
da++
da++
Table 8-24 STM cycle timing
DnMREQ,
DSEQ
N cycle
I cycle
N cycle
S cycle
S cycle
S cycle
ARM DDI 0165B
WDATA
R
R
R’
-
R’’
R’’’