SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 224
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 224 of 290
- Download datasheet (5Mb)
Signal Descriptions
A.3
A-4
Data memory interface signals
The data memory interface signals are shown in Table A-3.
Name
DA[31:0]
Data address
DABORT
Data abort
RDATA [31:0]
Read data
WDATA [31: 0]
Write data
DBGDEWPT
Data watchpoint
DLOCK
Data lock
DMAS[1:0]
Data memory
access size
DMORE
Data more
DnMREQ
Not data memory
request
Copyright © 2000 ARM Limited. All rights reserved.
Direction
Output
Input
Input
Output
Input
Output
Output
Output
Output
Description
The processor data address bus.
This is an input that allows the memory system
to tell the processor that the requested data
memory access is not allowed.
This bus is used to transfer data between the
memory system and the processor during read
cycles (when DnRW is LOW).
This bus is used to transfer data between the
memory system and the processor during write
cycles (when DnRW is HIGH).
This is an input that allows external hardware to
halt the execution of the processor for debug
purposes. If HIGH at the end of a data memory
request cycle, it causes the ARM9E-S to enter
debug state.
If HIGH, then any data memory access in the
following cycle is locked, and the memory
controller must wait until DLOCK goes LOW
before allowing another device to access the
memory.
These encode the size of a data memory access
in the following cycle. A word access is
encoded as 10 (binary), a halfword access as 0l,
and a byte access as 00. The encoding 11 is
reserved.
If HIGH at the end of the cycle, then the data
memory access in the following cycle is
directly followed by a sequential data memory
access.
If LOW at the end the cycle, then the processor
requires a data memory access in the following
cycle.
Table A-3 Data memory interface signals
ARM DDI 0165B
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