SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 126
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 126 of 290
- Download datasheet (5Mb)
ARM9E-S Coprocessor Interface
6.4
6-10
MCRR/MRRC
ARM processor pipeline
WDATA[31:0]
RDATA[31:0]
INSTR[31:0]
CHSD[1:0]
CHSE[1:0]
InMREQ
MCRR
Figure 6-4.
First InMREQ is driven LOW to denote that the instruction on INSTR[31:0] is
entering the Decode stage of the pipeline. This causes the coprocessor to decode the
new instruction and drive CHSD[1:0] as required.
In the next cycle InMREQ is driven LOW to denote that the instruction has now been
issued to the Execute stage. If the condition codes pass, and the instruction is to be
executed, the PASS signal is driven HIGH and the CHSD[1:0] handshake bus is
examined by the core (it is ignored in all other cases).
For any successive Execute cycles the CHSE[1:0] handshake bus is examined. When
the LAST condition is observed, the instruction proceeds to its final Execute cycle. In
the case of an
(MCRR)
(MRRC)
PASS
CLK
and
Copyright © 2000 ARM Limited. All rights reserved.
MRRC
MCRR
MCRR/MRRC
cycles look very similar to
, the WDATA[31:0] bus is driven with the first register data during
Decode
Figure 6-4 ARM9E-S MCRR or MRRC transfer timing
GO
Execute
(GO)
STC
LAST
or
Data1 (Rd)
Execute
(LAST)
LDC
. An example is shown in
Data1
Ignored
Data2 (Rn)
Memory
(LAST)
Data2
ARM DDI 0165B
(LAST)
Write
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