SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 170

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Times
8.5
8-10
Branch and exchange
or ARM
2.
3.
Table 8-6 shows the cycle timings, where:
i
A Branch and Exchange (
1.
i’
t’
Cycle
1
2
3
During the first cycle, the ARM9E-S extracts the branch destination and the new
core state while performing a prefetch from the current PC. This prefetch is
performed in all cases, because by the time the decision to take the branch has
been reached, it is already too late to prevent the prefetch. In the case of
BLX<register>
BLX<immediate>
changed. If the previous instruction requested a memory access (and there is no
interlock in the case of
cycle.
During the second cycle, the ARM9E-S performs a fetch from the branch
destination, using the new instruction width, dependent on the state that has been
selected. If the link bit is set, the return address to be stored in r14 is calculated.
During the third cycle, the ARM9E-S performs a fetch from the destination +2 or
+4 dependent on the new specified state, refilling the instruction pipeline.
Copyright © 2000 ARM Limited. All rights reserved.
BLX <immediate>
IA
pc’
pc’ + i’
pc’ + 2i’
Is the instruction width before the
Is the instruction width after the
Is the state of the ITBIT signal after the
InMREQ,
ISEQ
N cycle
S cycle
S cycle
, the branch destination new state comes from the register. For
BX
the destination is calculated as a PC offset. The state is always
), Branch, Link and Exchange register (
BX
operation takes three cycles, and is similar to a Branch:
,
BLX <register>
INSTR
(pc + 2i)
(pc’)
(pc’ + i’)
(pc’ + 2i’)
Table 8-6 Branch and exchange cycle timing
BX/BLX
ITBIT
t’
t’
t’
BX/BLX
), the data is transferred in this
BX/BLX
instruction.
-
DA
-
-
instruction.
I cycle
DnMREQ,
DSEQ
I cycle
I cycle
instruction.
BLX <register>
ARM DDI 0165B
RDATA/
WDATA
-
-
-
BX
and
)