SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 143
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 143 of 290
- Download datasheet (5Mb)
ARM DDI 0165B
Scan chain 2
In halt mode debug a request on one of the external debug interface signals, or on an
internal functional unit known as the EmbeddedICE-RT logic, forces the ARM9E-S into
debug state. The events that activate debug are:
•
•
•
•
The internal state of the ARM9E-S is examined using the JTAG serial interface, that
allows instructions to be serially inserted into the core pipeline without using the
external data bus. So, for example, when in debug state, a store multiple (
inserted into the instruction pipeline, and this exports the contents of the ARM9E-S
registers. This data can be serially shifted out without affecting the rest of the system.
a breakpoint (a given instruction fetch)
a watchpoint (a data access)
an external debug request
scanned debug request (a debug request scanned into the EmbeddedICE-RT delay
control register).
EmbeddedICE-RT
Copyright © 2000 ARM Limited. All rights reserved.
ARM9E-S
TAP controller
ARM9E-S
Scan chain 1
Figure 7-2 ARM9E-S block diagram
Debug Interface and EmbeddedICE-RT
ARM9E-S
core
STM
) can be
7-5
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