SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 480

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

31.4.2
31.4.3
31.4.3.1
31.4.3.2
480
480
SAM9G35
SAM9G35
Memory Peripherals
Handshaking Interface
Software Handshaking
Chunk Transactions
Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting
hmastlock for the duration of a DMAC transfer, buffer, or transaction (single or chunk). Channel
locking is asserted for the duration of bus locking at a minimum.
Figure 31-3 on page 478
eral. There is no handshaking interface with the DMAC, and therefore the memory peripheral
can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately
without waiting for a transaction request. The alternative to not having a transaction-level hand-
shaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the
channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait
states onto the bus until it is ready; it is not recommended that more than 16 wait states be
inserted onto the bus. By using the handshaking interface, the peripheral can signal to the
DMAC that it is ready to transmit/receive data, and then the DMAC can access the peripheral
without the peripheral inserting wait states onto the bus.
Handshaking interfaces are used at the transaction level to control the flow of single or chunk
transfers. The operation of the handshaking interface is different and depends on whether the
peripheral or the DMAC is the flow controller.
The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to trans-
fer/accept data over the AMBA bus. A non-memory peripheral can request a DMAC transfer
through the DMAC using one of two handshaking interfaces:
Software selects between the hardware or software handshaking interface on a per-channel
basis. Software handshaking is accomplished through memory-mapped registers, while hard-
ware handshaking is accomplished using a dedicated handshaking interface.
When the slave peripheral requires the DMAC to perform a DMAC transaction, it communicates
this request by sending an interrupt to the CPU or interrupt controller.
The interrupt service routine then uses the software registers to initiate and control a DMAC
transaction. These software registers are used to implement the software handshaking
interface.
The SRC_H2SEL/DST_H2SEL bit in the DMAC_CFGx channel configuration register must be
set to zero to enable software handshaking.
When the peripheral is not the flow controller, then the last transaction register DMAC_LAST is
not used, and the values in these registers are ignored.
Writing a 1 to the DMAC_CREQ[2x] register starts a source chunk transaction request, where x
is the channel number. Writing a 1 to the DMAC_CREQ[2x+1] register starts a destination chunk
transfer request, where x is the channel number.
Upon completion of the chunk transaction, the hardware clears the DMAC_CREQ[2x] or
DMAC_CREQ[2x+1].
• Hardware handshaking
• Software handshaking
shows the DMAC transfer hierarchy of the DMAC for a memory periph-
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11