SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 429

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30.4.2
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Low-power DDR1-SDRAM Initialization
After initialization, the SDR-SDRAM device is fully functional.
The initialization sequence is generated by software. The low-power DDR1-SDRAM devices are
initialized by the following sequence:
A minimum pause of 200 μs will be provided to precede any signal toggle.
Note:
10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register (see
1. Program the memory device type into the Memory Device Register (see
2. Program the features of the low-power DDR1-SDRAM device into the Configuration
3. Program temperature compensated self refresh (tcr), Partial array self refresh (pasr)
4. An NOP command will be issued to the low-power DDR1-SDRAM. Program NOP com-
5. An all banks precharge command is issued to the low-power DDR1-SDRAM. Program
6. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command
7. An Extended Mode Register set (EMRS) cycle is issued to program the low-power
8. A Mode Register set (MRS) cycle is issued to program the parameters of the low-power
page
requires a refresh every 15.625 μs or 7.81 μs. With a 100 MHz frequency, the refresh
timer count register must to be set with (15.625*100 MHz) = 1562 i.e. 0x061A or
(7.81*100 MHz) = 781 i.e. 0x030d
on page
Register: asynchronous timing (trc, tras, etc.), number of columns, rows, banks, cas
latency. See
30.7.5 on page
and Drive strength (ds) into the Low-power Register. See
mand into the Mode Register, the application must set Mode to 1 in the Mode Register
(see
address to acknowledge this command. Now clocks which drive DDR1-SDRAM device
are enabled.
all banks precharge command into the Mode Register, the application must set Mode to
2 in the Mode Register (See
any low-power DDR1-SDRAM address to acknowledge this command
(CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register
(see
SDRAM location twice to acknowledge these commands.
DDR1-SDRAM parameters (TCSR, PASR, DS). The application must set Mode to 5 in
the Mode Register (see
SDRAM to acknowledge this command. The write address must be chosen so that
BA[1] is set to 1 BA[0] is set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows,
9 columns, 4 banks) bank address, the low-power DDR1-SDRAM write access should
be done at address 0x20800000.
DDR1-SDRAM devices, in particular CAS latency, burst length. The application must
set Mode to 3 in the Mode Register (see
write access to the low-power DDR1-SDRAM to acknowledge this command. The write
address must be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128
MB low-power DDR1-SDRAM (12 rows, 9 columns, 4 banks) bank address, the
SDRAM write access should be done at the address 0x20000000. The application must
go into Normal Mode, setting Mode to 0 in the Mode Register (see
This address is for example purposes only. The real address is dependent on implementation in
the product.
Section 30.7.1 on page
Section 30.7.1 on page
457). (Refresh rate = delay between refresh cycles). The SDR-SDRAM device
467).
Section 30.7.3 on page
463.
Section 30.7.1 on page
Section 30.7.1 on page
456). Perform a write access to any DDR1-SDRAM
456). Perform a write access to any low-power DDR1-
458,
Section 30.7.1 on page
Section 30.7.4 on page 461
456) and perform a write access to the
456). Perform a write access to
Section 30.7.7 on page
456) and perform a
Section 30.7.1 on
and
SAM9G35
SAM9G35
Section 30.7.8
Section
465.
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