SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 474

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

31.2.1
474
474
SAM9G35
SAM9G35
DMA Controller 0
The DMA controller can handle the transfer between peripherals and memory and so receives
the triggers from the peripherals listed below. The hardware interface numbers are also given in
Table
Table 31-1.
Instance Name
HSMCI0
SPI0
SPI0
USART0
USART0
USART1
USART1
TWI0
TWI0
TWI2
TWI2
UART0
UART0
SSC
SSC
• Transfer Initiation
• Interrupt
• Two Masters
• Embeds 8 channels
• 64-byte FIFO for channel 0, 16-byte FIFO for Channels 1 to 7
• Features:
– Support for Software handshaking interface. Memory mapped registers can be used
– Programmable Interrupt generation on DMA Transfer completion Block Transfer
– Linked List support with Status Write Back operation at End of Transfer
– Word, HalfWord, Byte transfer support.
– Memory to Memory transfer
– Peripheral to memory
– Memory to peripheral
31-1.
to control the flow of a DMA transfer in place of a hardware handshaking interface
completion, Single/Multiple transaction completion or Error condition
DMA Channel Definition
T/R
RX/TX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
10
13
DMA Channel HW
interface Number
0
1
2
3
4
5
6
7
8
9
11
12
14
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11