SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 766
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SAM9G10
Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(1274 pages)
2.SAM9261.pdf
(43 pages)
3.SAM9G10.pdf
(750 pages)
4.SAM9G10.pdf
(39 pages)
Specifications of SAM9G10
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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38.8.7
38.8.8
38.8.9
766
766
SAM9G35
SAM9G35
Using the DMA Controller (DMAC)
SMBUS Quick Command (Master Mode Only)
Read-write Flowcharts
Figure 38-13
the use of internal addresses to access the device.
Figure 38-13. Internal Address Usage
The use of the DMAC significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequence.
The TWI interface can perform a Quick Command:
Figure 38-14. SMBUS Quick Command
The following flowcharts shown in
38-18 on page
read and write operations. A polling or interrupt method can be used to check the status bits.
The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.
3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit
1. Initialize the DMAC (channels, memory pointers, size, etc.);
1. Configure the master mode (DADR, CKDIV, etc.).
1. Enable the DMAC.
1. Wait for the DMAC flag.
1. Disable the DMAC.
1. Configure the master mode (DADR, CKDIV, etc.).
2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to
3. Start the transfer by setting the QUICK bit in the TWI_CR.
address)
be sent.
below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates
770,
R
S
T
A
T
M
S
B
Figure 38-19 on page 771
Address
Device
TXCOMP
0
Write QUICK command in TWI_CR
TXRDY
S
B
TWD
L
W
W
R
T
E
R
I
/
C
A
K
WORD ADDRESS
Figure 38-16 on page
M
S
B
S
FIRST
DADR
A
C
K
and
WORD ADDRESS
SECOND
Figure 38-20 on page 772
R/W
768,
L
S
B
C
A
K
A
Figure 38-17 on page
DATA
P
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
A
C
K
O
S
T
P
give examples for
769,
Figure
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