SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 590

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

• RX_SETUP/ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enabled
0 = Received SETUP/Error Flow Interrupt is masked.
1 = Received SETUP/Error Flow Interrupt is enabled.
• STALL_SNT/ERR_CRISO/ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled
0 = Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked.
1 = Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled.
• NAK_IN/ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enabled
0 = NAKIN Interrupt is masked.
1 = NAKIN/Bank Flush Error Interrupt is enabled.
• NAK_OUT: NAKOUT Interrupt Enabled
0 = NAKOUT Interrupt is masked.
1 = NAKOUT Interrupt is enabled.
• BUSY_BANK: Busy Bank Interrupt Enabled
0 = BUSY_BANK Interrupt is masked.
1 = BUSY_BANK Interrupt is enabled.
• SHRT_PCKT: Short Packet Interrupt Enabled
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For OUT endpoints: an interrupt is sent when all banks are busy.
For IN endpoints: an interrupt is sent when all banks are free.
For OUT endpoints: send an Interrupt when a Short Packet has been received.
0 = Short Packet Interrupt is masked.
1 = Short Packet Interrupt is enabled.
For IN endpoints: a Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling a BULK or
INTERRUPT end of transfer or an end of isochronous (micro-)frame data, but only if the UDPHS_DMACONTROLx
register END_B_EN and UDPHS_EPTCTLx register AUTO_VALID bits are also set.
SAM9G35
SAM9G35
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11