SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 560

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

33.6.10
33.6.11
33.6.12
560
560
SAM9G35
SAM9G35
Speed Identification
USB V2.0 High Speed Global Interrupt
Endpoint Interrupts
The high speed reset is managed by the hardware.
At the connection, the host makes a reset which could be a classic reset (full speed) or a high
speed reset.
At the end of the reset process (full or high), the ENDRESET interrupt is generated.
Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of
the device.
Interrupts are defined in
in
Interrupts are enabled in UDPHS_IEN (see
and individually masked in UDPHS_EPTCTLENBx (see
Control Enable
Table 33-5.
SHRT_PCKT
BUSY_BANK
NAK_OUT
NAK_IN/ERR_FLUSH
STALL_SNT/ERR_CRISO/ERR_NB_TRA
RX_SETUP/ERR_FL_ISO
TX_PK_RD /ERR_TRANS
TX_COMPLT
RX_BK_RDY
ERR_OVFLW
MDATA_RX
DATAX_RX
Section 33.7.4 ”UDPHS Interrupt Status Register”
Endpoint Interrupt Source Masks
Register”).
Section 33.7.3 ”UDPHS Interrupt Enable Register”
Section 33.7.3 ”UDPHS Interrupt Enable
Short Packet Interrupt
Busy Bank Interrupt
NAKOUT Interrupt
NAKIN/Error Flush Interrupt
Stall Sent/CRC error/Number of Transaction
Error Interrupt
Received SETUP/Error Flow Interrupt
TX Packet Read/Transaction Error Interrupt
Transmitted IN Data Complete Interrupt
Received OUT Data Interrupt
Overflow Error Interrupt
MDATA Interrupt
DATAx Interrupt
(UDPHS_INTSTA).
Section 33.7.12 ”UDPHS Endpoint
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
(UDPHS_IEN) and
Register”)