SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1260

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Revision History
11053B–ATARM–22-Sep-11
Doc. Rev.
11053B
Doc. Rev.
11053A
Comments
System Controller:
Figure
ADC:
Section 41. “Analog-to-Digital Converter (ADC)”
DMAC:
FIFO size table removed from , as the size depends on DMAC0 (see
DMAC1 (see
MATRIX:
Section 26.7.6.1 “EBI Chip Select Assignment
PMC:
Section 22.2 “Embedded
Then
Figure
Section 22.3 “Master Clock
Section 22.7 “LP-DDR/DDR2
Section 22.13.11 “PMC Master Clock
UHPHS:
Section 32.2.2
introducing sentence.
Electrical Characteristics:
Section 46.12 “USB Transceiver Characteristics”
41-23 and Table 41-46).
Errata:
Section 49.1 “Boot Sequence Controller (BSC)”
programmer description.
Section 49.5 “USB High Speed Host Port (UHPHS)” removed.
Comments
1st issue
- Prescaler /1,/2,/4,.../64 --> Prescaler /1,/2,/3,/4,.../64 (for Master Clock Controller).
- SysClk DDR --> 2x MCK, and connection added above with /2 block and DDRCK.
- Value 7 for PRES field no more reserved, now with CLOCK_DIV3, Selected clock divided by 3.
- MDIV field, references to ‘SysClk DDR’ removed (x4).
DDR system clock --> DDR clock.
7-1,
22-2,
“SAM9G35 System Controller Block Diagram”
“General Clock Block Diagram”
Section 31.2.2 “DMA Controller
“OHCI”,
In the tables that follow, the most recent version appears first. “rfo” denotes expert input during
the update process
Figure 32-2 “Board Schematics to Interface UHP Device Controller”
Characteristics”,
Controller”, ...and the division by 6 --> ...and the division by 3.
Clock”, sentences with ‘ SysClk’ removed.
Register”:
266MHz DDR system clock --> 133MHz DDR system clock.
:
1”).
Register”, description of NFD0_ON_D16 bitfield updated.
added as the BSC_CR register does not comply with the
updated to show Touchscreen information.
added (extracted from SAM9G20 - 6384E: Section 41.7, Figure
, DDR sysclk --> DDRCK.
Section 31.2.1 “DMA Controller
added, with an
0”) and
SAM9G35
Change
Request
Ref.
rfo
7987
8004
8008
7975
rfo
7974
8006
8016
8016
7996
rfo
Change
Request
Ref.
1259