SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 557

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 33-15. Data OUT Transfer for an Endpoint with Two Banks
33.6.9.13
Figure 33-16. Bank Management, Example of Three Transactions per Microframe
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
USB Bus
Packets
Virtual RX_BK_RDY
Bank 0
Virtual RX_BK_RDY
Bank 1
RX_BK_RDY = (virtual bank 0 | virtual bank 1)
(UDPHS_EPTSTAx)
FIFO (DPR)
Bank 0
FIFO (DPR)
Bank 1
USB bus
Transactions
Microcontroller FIFO
(DPR) Access
t = 0
High Bandwidth Isochronous Endpoint OUT
Host sends first data payload
Token OUT
Set by Hardware,
Data payload written
in FIFO endpoint bank 0
MDATA0
RX_BK_RDY
Write by UDPHS Device
USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192
Mb/s (24 MB/s): 3x1024 data bytes per microframe.
To support such a rate, two or three banks may be used to buffer the three consecutive data
packets. The microcontroller (or the DMA) should be able to empty the banks very rapidly (at
least 24 MB/s on average).
NB_TRANS field in UDPHS_EPTCFGx register = Number Of Transactions per Microframe.
If NB_TRANS > 1 then it is High Bandwidth.
MDATA1
Data OUT 1
Data OUT 1
Read Bank 1
DATA2
ACK
Read by Microcontroller
Set by Hardware
Data Payload written
in FIFO endpoint bank 1
t = 52.5 μs
(40% of 125 μs)
Interrupt pending
Microcontroller reads Data 1 in bank 0,
Host sends second data payload
Data OUT 1
Token OUT
Read Bank 2
Write by Hardware
Data OUT 2
Data OUT 2
Cleared by Firmware
Read Bank 3
ACK
t = 125 μs
Token OUT
Read by Microcontroller
Microcontroller reads Data 2 in bank 1,
Host sends third data payload
MDATA0
Interrupt pending
Data OUT 2
RX_BK_RDY
Write in progress
Data OUT 3
Data OUT 3
MDATA1
Read Bank 1
SAM9G35
SAM9G35
Cleared by Firmware
USB line
DATA2
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