SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1067
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SAM9G10
Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(1274 pages)
2.SAM9261.pdf
(43 pages)
3.SAM9G10.pdf
(750 pages)
4.SAM9G10.pdf
(39 pages)
Specifications of SAM9G10
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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45.6.2
45.6.2.1
45.6.2.2
45.6.2.3
45.6.2.4
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
DMA Software Operations
DMA Channel Descriptor (DSCR) Alignment and Structure
Programming a DMA Channel
Disabling a DMA channel
DMA Dynamic Linking of a New Transfer Descriptor
The DMA Channel Descriptor (DSCR) must be word aligned.
The DMA Channel Descriptor structure contains three fields:
Table 45-4.
DSCR + 0x4
DSCR + 0x8
• DSCR.CHXADDR: Frame Buffer base address register
• DSCR.CHXCTRL: Transfer Control register
• DSCR.CHXNEXT: Next Descriptor Address register
1. Check the status of the channel reading the CHXCHSR register.
2. Write the channel descriptor (DSCR) structure in the system memory by writing
3. If more than one descriptor is expected, the DFETCH field of DSCR.CHXCTRL is set to
4. Write the DSCR.CHXNEXT register with the address location of the descriptor struc-
5. Enable the relevant channel by writing one to the CHEN field of the CHXCHER register.
6. An interrupt may be raised if unmasked when the descriptor has been loaded.
1. Clear the DFETCH bit in the DSCR.CHXCTRL field of the DSCR structure will disable
2. Set the DSCR.CHXNEXT field of the DSCR structure will disable the channel at the
3. Writing one to the CHDIS field of the CHXCHDR register will disable the channel at the
4. Writing one to the CHRST field of the CHXCHDR register will disable the channel
5. Poll CHSR field in the CHXCHSR register until the channel is successfully disabled.
1. Write the new descriptor structure in the system memory.
2. Write the address of the new structure in the CHXHEAD register.
3. Add the new structure to the queue of descriptors by writing one to the A2QEN field of
4. The new descriptor will be added to the queue on the next frame.
5. An interrupt will be raised if unmasked, when the head descriptor structure has been
System Memory
DSCR.CHXADDR Frame base address, DSCR.CHXCTRL channel control and
DSCR.CHXNEXT next descriptor location.
one to enable the descriptor fetch operation.
ture and set DFETCH field of the DSCR.CHXCTRL register to one.
the channel at the end of the frame.
end of the frame.
end of the frame.
immediately. This may occur in the middle of the image.
the CHXCHER register.
loaded by the DMA channel.
DSCR + 0x0
DMA Channel Descriptor Structure
CTRL
NEXT
Structure Field for channel CHX
ADDR
SAM9G35
SAM9G35
1067
1067
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