SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1099
SAM9G10
Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(1274 pages)
2.SAM9261.pdf
(43 pages)
3.SAM9G10.pdf
(750 pages)
4.SAM9G10.pdf
(39 pages)
Specifications of SAM9G10
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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45.7.1
Name:
Address:
Access:
Reset:
• CLKPOL: LCD Controller Clock Polarity
0: Data/Control signals are launched on the rising edge of the Pixel Clock.
1: Data/Control signals are launched on the falling edge of the Pixel Clock.
• CLKSEL: LCD Controller Clock Source Selection
0: The Asynchronous output stage of the LCD controller is fed by MCK.
1: The Asynchronous output state of the LCD controller is fed by 2x MCK.
• CLKPWMSEL: LCD Controller PWM Clock Source Selection
0: The slow clock is selected and feeds the PWM module.
1: The system clock is selected and feeds the PWM module.
• CGDISBASE: Clock Gating Disable Control for the Base Layer
0: Automatic Clock Gating is enabled for the Base Layer.
1: Clock is running continuously.
• CGDISOVR1: Clock Gating Disable Control for the Overlay 1 Layer
0: Automatic Clock Gating is enabled for the Overlay 1 Layer.
1: Clock is running continuously.
• CGDISHEO: Clock Gating Disable Control for the High End Overlay
0: Automatic Clock Gating is enabled for the High End Overlay Layer.
1: Clock is running continuously.
• CGDISHCR: Clock Gating Disable Control for the Hardware Cursor Layer
0: Automatic Clock Gating is enabled for the Hardware Cursor Layer.
1: Clock is running continuously.
• CLKDIV: LCD Controller Clock Divider
8 bit width clock divider for pixel clock LCD_PCLK.
pixel_clock = selected_clock/(CLKDIV+2)
where selected_clock is equal to system_clock when CLKSEL field is set to 0 and system_clock2x when CLKSEL is set to
one.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
31
23
15
–
–
7
–
LCD Controller Configuration Register 0
LCDC_LCDCFG0
0xF8038000
Read-write
0x00000000
30
22
14
–
–
6
–
29
21
13
–
–
5
–
CGDISHCR
28
20
12
–
4
–
CLKDIV
CLKPWMSEL
CGDISHEO
27
19
11
–
3
CLKSEL
26
18
10
–
–
2
CGDISOVR1
25
17
–
9
1
–
SAM9G35
SAM9G35
CGDISBASE
CLKPOL
24
16
–
8
0
1099
1099
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