SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1071

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

45.6.3.5
45.6.4
45.6.4.1
Table 45-10. 1 bpp memory mapping, little endian organization
45.6.4.2
Table 45-11. 2 bpp memory mapping, little endian organization
45.6.4.3
Table 45-12. 4 bpp memory mapping, little endian organization
45.6.4.4
Table 45-13. 8 bpp memory mapping, little endian organization
45.6.4.5
Table 45-14. 12 bpp memory mapping, little endian organization
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Mem addr
Bit
Pixel 1 bpp
Mem addr
Bit
Pixel 2 bpp
Mem addr
Bit
Pixel 4 bpp
Mem addr
Bit
Pixel 8 bpp
Mem addr
Bit
Pixel 12 bpp
RGB Frame Buffer Memory Bitmap
0x3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
p3
1
0x3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Window Attributes Software Operation
1 bpp Through Color Lookup Table
2 bpp Through Color Lookup Table
4 bpp Through Color Lookup Table
8 bpp Through Color Lookup Table
12 bpp Memory Mapping, RGB 4:4:4
0x3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0x3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0x3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
p15
p3
0
p7
–
p2
9
p14
p2
8
p3
p2
7
1. When required, write the overlay attributes configuration registers.
2. Set UPDATEEN field of the CHXCHER register.
3. Poll UPDATESR field in the CHXCHSR, the update applies when that field is reset.
p13
p2
6
R1[3:0]
p6
p2
5
p12
p2
4
0x2
p2
3
0x2
0x2
0x2
0x2
p11
p2
2
G1[3:0]
p5
p2
1
p10
p2
0
p2
p1
9
p9
p1
8
B1[3:0]
p4
p1
7
p8
p1
6
0x1
p1
5
0x1
0x1
0x1
0x1
p7
p1
4
p3
–
p1
3
p6
p1
2
p1
p1
1
p5
p1
0
R0[3:0]
p2
p9 p8 p7 p6 p5 p4 p3 p2 p1 p0
p4
8
8
8
8
8
0x0
7
0x0
7
0x0
7
0x0
7
0x0
7
p3
6
6
6
6
G0[3:0]
6
p1
5
5
5
5
5
SAM9G35
SAM9G35
p2
4
4
4
4
4
p0
3
3
3
3
3
p1
2
2
2
2
B0[3:0]
2
p0
1
1
1
1
1
1071
1071
p0
0
0
0
0
0