ATtiny461 Automotive Atmel Corporation, ATtiny461 Automotive Datasheet - Page 88
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ATtiny461 Automotive
Manufacturer Part Number
ATtiny461 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY261_AUTOMOTIVE.pdf
(11 pages)
3.ATTINY261_AUTOMOTIVE.pdf
(16 pages)
4.ATTINY261_AUTOMOTIVE.pdf
(226 pages)
Specifications of ATtiny461 Automotive
Flash (kbytes)
4 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
256
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY261_AUTOMOTIVE PDF datasheet #2
- ATTINY261_AUTOMOTIVE PDF datasheet #3
- ATTINY261_AUTOMOTIVE PDF datasheet #4
- Current page: 88 of 226
- Download datasheet (5Mb)
14.10.7
88
ATtiny261/ATtiny461/ATtiny861
TIFR – Timer/Counter0 Interrupt Flag Register
• Bit 4– OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
The OCF0A is also set in 16-bit mode when a Compare Match occurs between the Timer/Coun-
ter and 16-bit data in OCR0B/A. The OCF0A is not set in Input Capture mode when the Output
Compare Register OCR0A is used as an Input Capture Register.
• Bit 3 – OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
The OCF0B is not set in 16-bit Output Compare mode when the Output Compare Register
OCR0B is used as the high byte of the 16-bit Output Compare Register or in 16-bit Input Cap-
ture mode when the Output Compare Register OCR0B is used as the high byte of the Input
Capture Register.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
• Bits 0 – ICF0: Timer/Counter0, Input Capture Flag
This flag is set when a capture event occurs on the ICP0 pin. When the Input Capture Register
(ICR0) is set to be used as the TOP value, the ICF0 flag is set when the counter reaches the
TOP value.
ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF0 can be cleared by writing a logic one to its bit location.
Bit
0x38 (0x58)
Read/Write
Initial Value
OCF1D
R/W
7
0
OCF1A
R/W
6
0
OCF1B
R/W
5
0
OCF0A
R/W
4
0
OCF0B
R/W
3
0
TOV1
R/W
2
0
TOV0
R/W
1
0
ICF0
R
0
0
7753F–AVR–01/11
TIFR
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