ATtiny461 Automotive Atmel Corporation, ATtiny461 Automotive Datasheet - Page 28

• Manufacturer Part Number: ATtiny461 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny461 Automotive

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7.5
28
High Frequency PLL Clock - PLL
ATtiny261/ATtiny461/ATtiny861
Figure 7-3.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table
Table 7-3.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to
32
There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator
for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as
a system clock source, by programming the CKSEL fuses to ‘0001’, it is divided by four like
shown in
SUT fuses as shown in
Table 7-4.
Table 7-5.
SUT1..0
SUT1..0
for details.
00
01
10
11
00
01
10
11
7-3.
Table
14CK + 16K (16384) + 64 ms
14CK + 16K (16384) + 4 ms
Power-down and Power-save
Start-up Time from Power
14CK + 1K (1024) + 64 ms
CKSEL3..0
14CK + 1K (1024) + 4 ms
External Clock Drive Configuration
Start-up Times for the External Clock Selection
PLLCK Operating Modes
Start-up Times for the PLLCK
7-4. When this clock source is selected, start-up times are determined by the
0001
Start-up Time from
Down
CLK
Table
6 CK
6 CK
6 CK
EXTERNAL
7-5. See also
SIGNAL
CLOCK
Power-On-Reset (V
“PCK Clocking System” on page
Additional Delay from
Additional Delay from
Reserved
14CK + 64 ms
14CK + 4 ms
CLKI
GND
4 ms
4 ms
4 ms
4 ms
Reset
14CK
Nominal Frequency
CC
“System Clock Prescaler” on page
= 5.0V) Recommended usage
16 MHz
BOD enabled
Fast rising power
Slowly rising power
BOD enabled
Fast rising power
Slowly rising power
Slowly rising power
Recommended Usage
26.
7753F–AVR–01/11