ATtiny461 Automotive Atmel Corporation, ATtiny461 Automotive Datasheet - Page 79

• Manufacturer Part Number: ATtiny461 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny461 Automotive

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

14.7.1
14.7.2
14.8
7753F–AVR–01/11
Timer/Counter Timing Diagrams
Compare Match Blocking by TCNT0 Write
Using the Output Compare Unit
Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location.
Figure 14-4
Figure 14-4. Output Compare Unit, Block Diagram
All CPU write operations to the TCNT0H/L Register will block any Compare Match that occur in
the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A/B to be
initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter
clock is enabled.
Since writing TCNT0H/L will block all Compare Matches for one timer clock cycle, there are risks
involved when changing TCNT0H/L when using the Output Compare Unit, independently of
whether the Timer/Counter is running or not. If the value written to TCNT0H/L equals the
OCR0A/B value, the Compare Match will be missed.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
shows the count sequence close to the MAX value.
Figure 14-5. Timer/Counter Timing Diagram, no Prescaling
Figure 14-6
TCNTn
(clk
TOVn
clk
clk
I/O
I/O
Tn
/1)
shows a block diagram of the Output Compare unit.
shows the same timing data, but with the prescaler enabled.
Figure 14-5
MAX - 1
OCRnx
contains timing data for basic Timer/Counter operation. The figure
ATtiny261/ATtiny461/ATtiny861
=
(8/16-bit Comparator )
DATA BUS
OCFnx (Int.Req.)
MAX
BOTTOM
TCNTn
T0
) is therefore shown as a
BOTTOM + 1
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