ATtiny461 Automotive Atmel Corporation, ATtiny461 Automotive Datasheet
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ATtiny461 Automotive
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ATtiny461 Automotive Summary of contents
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Features • High Performance, Low Power AVR • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – General Purpose Working Registers – Fully Static Operation • Non-volatile Program and Data Memories – ...
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Pin Configurations ® Figure 1-1. Pinout Atmel ATtiny24/44/84 (PCINT8/XTAL1) PB0 (PCINT9/XTAL2) PB1 (PCINT11/RESET/dW) PB3 (PCINT10/INT0/OC0A/CKOUT) PB2 (PCINT7/ICP/OC0B/ADC7) PA7 (PCINT6/OC1A/SDA/MOSI/ADC6) PA6 (ADC4/USCK/SCL/T1/PCINT4) PA4 (ADC3/T0/PCINT3) PA3 (ADC2/AIN1/PCINT2) PA2 (ADC1/AIN0/PCINT1) PA1 (ADC0/AREF/PCINT0) PA0 NOTE Bottom pad should be soldered to ground. DNC: ...
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Overview The Atmel enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATtiny24/44/84 achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure ...
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The Atmel ters. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving ...
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Pin Descriptions 2.3.1 VCC Supply voltage. 2.3.2 GND Ground. 2.3.3 Port B (PB3...PB0) Port 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with ...
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Resources A comprehensive set of development tools, driver and application notes, and datasheets are available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the ...
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CPU Core 5.1 Overview This section discusses the Atmel CPU core is to ensure correct program execution. The CPU must, therefore, be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.2 Architectural Overview Figure 5-1. In ...
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The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle arithmetic logic unit (ALU) operation typ- ical ALU operation, two operands are output from the register ...
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The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 5.4.1 SREG – AVR Status Register Bit 0x3F (0x5F) Read/Write Initial Value • Bit 7 ...
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General Purpose Register File The register file is optimized for the Atmel achieve the required performance and flexibility, the following input/output schemes are sup- ported by the register file: • One 8-bit output operand and one 8-bit result input ...
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Figure 5-3. X-register Y-register Z-register In the different addressing modes, these address registers have functions as fixed displace- ment, automatic increment, and automatic decrement (see the instruction set summary for details). 5.6 Stack Pointer The stack is mainly used for ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The Atmel clock source for the chip. No internal clock division is used. Figure 5-4 on page 12 enabled by the Harvard architecture and the ...
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When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are dis- abled. The user software can write a logical one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example C Code Example 5.8.1 Interrupt Response Time The interrupt execution response for ...
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Memories This section describes the different memories in the Atmel tecture has two main memory spaces, the data memory space and the program memory space. In addition, the Atmel ATtiny24/44/84 features an EEPROM memory for data storage. All three ...
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When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and 128/256/512 bytes of internal data SRAM in ...
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EEPROM Data Memory The Atmel nized as a separate data space in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU ...
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Erase To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (pro- gramming time is given ...
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Assembly Code Example C Code Example Note: 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set Programming mode r16, (0<<EEPM1)|(0<<EEPM0) ldi EECR, r16 out ; Set up address (r17) in address ...
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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execu- tion of these functions. Assembly Code Example C Code Example Note: 6.3.6 ...
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I/O Memory The I/O space definition of the Atmel page All Atmel ATtiny24/44/84 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 ...
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Register Description 6.5.1 EEARH – EEPROM Address Register Bit 0x1F (0x3F) Read/Write Initial Value • Bits 7..1 – Res: Reserved Bits These are reserved bits in the ATtiny24/44/84, and will always read as zero. • Bit 0 – EEAR8: ...
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Bit 7 – Res: Reserved Bit This bit is reserved for future use, and will always read Atmel compatibility with future AVR mask out this bit. • Bit 6 – Res: Reserved Bit This bit is ...
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Bit 0 – EERE: EEPROM Read Enable The EEPROM read enable signal, EERE, is the read strobe for the EEPROM. When the cor- rect address is set up in the EEAR register, the EERE bit must be written to ...
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System Clock and Clock Options 7.1 Clock Systems and their Distribution Figure 7-1 on page 25 All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not ...
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ADC Clock – clk ADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by their digital circuitry. This gives more accurate ADC conversion results. ...
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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 7-2. Either a quartz crystal or a ceramic resonator may be ...
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Table 7-4. CKSEL0 Notes: 7.5 Low-frequency Crystal Oscillator To use a 32.768kHz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting CKSEL fuses to “0110”. The crystal should be connected as ...
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Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 22-2 on page 180 device is shipped ...
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Figure 7-3. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 7-8 on page Table 7-8. SUT1.. When applying an external clock, sudden changes in the applied ...
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Internal Oscillator The 128kHz internal oscillator is a low power oscillator providing a 128kHz clock. The fre- quency is nominal at 3V and 25°C. This clock may be selected as the system clock by programming the CKSEL fuses ...
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Register Description 7.10.1 Oscillator Calibration Register – OSCCAL Bit 0x31 (0x51) Read/Write Initial Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value ...
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To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The Atmel consumption to the application’s requirements. 8.1 Sleep Modes Figure 7-1 on page 25 their distribution. The ...
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Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting ...
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When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60µs to ensure that the BOD is working correctly before the MCU continues executing code. BOD disable is controlled by the BODS (BOD Sleep) bit ...
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Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always ...
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Register Description 8.9.1 MCUCR – MCU Control Register The MCU Control Register contains control bits for power management. Bit Read/Write Initial Value • Bit 7 – BODS: BOD Sleep In order to disable BOD during sleep (see to logic ...
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PRR – Power Reduction Register Bit Read/Write Initial Value • Bits Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 3- PRTIM1: Power Reduction Timer/Counter1 ...
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System Control and Reset 9.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP ...
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Figure 9-1. 9.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in whenever V Reset, as well as to detect a failure in supply voltage. A POR circuit ensures ...
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Figure 9-3. TIME-OUT INTERNAL Table 9-1. Symbol V POT V PORMAX V PORMIN V CCRR V RST Note: 9.4 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses lon- ger ...
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Figure 9-4. 9.5 Brown-out Detection ATtiny24/44/84 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. ...
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Figure 9-6. 9.7 Internal Voltage Reference The Atmel Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 9.7.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time ...
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To prevent unintentional disabling of the watchdog or unintentional change of time-out period, two different safety levels are selected by the WDTON fuse, as shown in Table 9-2. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on ...
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Register Description 9.10.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 0x34 (0x54) Read/Write Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved ...
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If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is use- ful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, the next time-out will generate a ...
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Table 9-4. WDP3 Atmel ATtiny24/44/84 [Preliminary] 48 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 ...
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The following code example shows one assembly function and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. ...
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Interrupts This section describes the specifics of the interrupt handling as performed in Atmel ATtiny24/44/84. For a general explanation of the AVR Interrupt Handling” on page 10.1 Interrupt Vectors Table 10-1. Vector No. Atmel ATtiny24/44/84 [Preliminary] 50 12. Reset ...
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If the program never enables an interrupt source, the Interrupt Vectors are not used, and regu- lar program code can be placed at these locations. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ...
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External Interrupts The external interrupts are triggered by the INT0 pin or any of the PCINT11..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT11..0 pins are configured as outputs. This feature provides ...
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Register Description 11.2.1 MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 0x35 (0x55) Read/Write Initial Value • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit ...
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Bit 4– PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set and the I-bit in the Status Register (SREG) is set, pin change inter- rupt 0 is enabled. Any change on any enabled PCINT7..0 pin will ...
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Bits 3..0 – PCINT11..8: Pin Change Enable Mask 11..8 Each PCINT11..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is set (logical one) and the PCIE1 bit in GIMSK is set, pin ...
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I/O Ports 12.1 Overview All Atmel I/O ports. This means that the SBI and CBI instructions can be used to change direction of one port pin without unintentionally changing the direction of any other pin. The same applies when ...
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Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 12.2 Ports as General Digital I/O The ports are bi-directional I/O ports ...
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If PORTxn is written logical one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logical zero when the pin is configured as an output pin, the port pin ...
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Figure 12-3. Synchronization when Reading an Externally Applied Pin value Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock ...
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The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define the port pins from input with a pull-up assigned to port pin 4. The resulting ...
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If a logic high level (logical one) is present on an asynchronous external interrupt pin config- ured as "interrupt on rising edge, falling edge, or any logic change on pin" while the external interrupt is not enabled, the corresponding external ...
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Figure 12-5. Alternate Port Functions Note: Table 12-2 on page 63 indexes from signals are generated internally in the modules having the alternate function. Atmel ATtiny24/44/84 [Preliminary] 62 PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 Pxn ...
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Table 12-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function ...
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Alternate Functions of Port A The Port A pins with alternate function are shown in Table 12-3. • Port A, Bit 0 – ADC0/AREF/PCINT0 ADC0: Analog to Digital Converter, Channel 0 AREF: External Analog Reference for ADC. Pullup and ...
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Port A, Bit 1 – ADC1/AIN0/PCINT1 ADC1: Analog to Digital Converter, Channel 1 AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with ...
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Port A, Bit 6 – ADC6/DI/SDA/OC1A/PCINT6 ADC6: Analog to Digital Converter, Channel 6 SDA: Two-wire mode Serial Interface Data. DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin must be ...
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Table 12-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 12-6. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Overriding Signals for Alternate Functions in ...
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Alternate Functions of Port B The Port B pins with alternate function are shown in Table 12-7. • Port B, Bit 0 – XTAL1/PCINT8 XTAL1: Chip clock oscillator pin 1. Used for all chip clock sources except the internal ...
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Port B, Bit 3 – RESET/dW/PCINT11 RESET: External Reset input is active low and enabled by un-programming ("1") the RST- DISBL fuse. Pull-up is activated and output driver and digital input are deactivated when the pin is used as ...
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Table 12-9. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 1. 2. 12.4 Register Description 12.4.1 MCUCR – MCU Control Register . Bit Read/Write Initial Value • Bit 6 – PUD: Pull-up Disable When this ...
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DDRA – Port A Data Direction Register Bit 0x1A (0x3A) Read/Write Initial Value 12.4.4 PINA – Port A Input Pins Address Bit 0x19 (0x39) Read/Write Initial Value 12.4.5 PORTB – Port B Data Register Bit 0x18 (0x38) Read/Write Initial ...
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Timer/Counter0 with PWM 13.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period ...
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Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCR0A ...
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Signal description (internal signals): Depending on the mode of operation used, the counter is cleared, incremented, or decre- mented at each timer clock (clk source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = ...
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Figure 13-3. Output Compare Unit, Block Diagram The OCR0x registers are double buffered when using any of the pulse width modulation (PWM) modes. For the normal and clear timer on compare (CTC) modes of operation, the double buffering is disabled. ...
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Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved in changing TCNT0 when using the output compare unit, independently of whether ...
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The design of the output compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation, see 13.6.1 Compare Output Mode and Waveform Generation ...
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The timing diagram for the CTC mode is shown in (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 13-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can ...
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This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows the use of physically smaller external compo- nents (coils, capacitors, etc.), and hence reduces total system cost. In fast PWM ...
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The extreme values for the OCR0A register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to bottom, the out- put will be a narrow spike for each max+1 ...
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Figure 13-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period The timer/counter overflow flag (TOV0) is set each time the counter reaches bottom. The inter- rupt flag can be used to generate an interrupt each time the counter ...
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OCR0A changes its value from MAX MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the ...
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Figure 13-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f (clk TCNTn OCRnx Figure 13-11 on page 83 and fast PWM mode where OCR0A is TOP. Figure 13-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with (clk ...
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Register Description 13.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x30 (0x50) Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the output compare pin (OC0A) behavior. If one or both of ...
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Table 13-4 on page 85 to phase correct PWM mode. Table 13-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 ...
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Note: Table 13-4 correct PWM mode. Table 13-7. COM0A1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode ...
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TCCR0B – Timer/Counter Control Register B Bit 0x33 (0x53) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility ...
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Table 13-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...
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TIMSK0 – Timer/Counter 0 Interrupt Mask Register Bit 0x39 (0x59) Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 2- OCIE0B: Timer/Counter ...
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Bit 0– TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in timer/counter 0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical one ...
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Timer/Counter1 14.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare ...
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Figure 14-1. 16-bit Timer/Counter Block Diagram Note: 14.2.1 Registers The timer/counter (TCNT1), output compare registers (OCR1A/B), and input capture register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in ...
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The double buffered output compare registers (OCR1A/B) are compared with the timer/coun- ter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the output ...
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Accessing 16-bit Registers TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the Atmel CPU via the 8-bit data bus. The 16-bit registers must be byte accessed using two read or write operations. Each 16-bit timer ...
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It is important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions accessing the 16-bit register and the interrupt code updates the temporary register by accessing the same or any of the ...
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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example C Code Example Note: The ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 14-2. Counter Unit Block Diagram Signal description (internal signals): The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high ...
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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 14.6 Input Capture Unit The timer/counter incorporates an input capture unit that can ...
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The ICR1 register can only be written when using a waveform generation mode that utilizes the ICR1 register for defining the counter's top value. In these cases the waveform generation mode (WGM13:0) bits must be set before the top value ...
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Measurement of an external signal's duty cycle requires that the trigger edge be changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 register has been read. After a change of the ...
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The OCR1x register is double buffered when using any of the twelve pulse width modulation (PWM) modes. For the normal and clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update ...
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Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 14.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that no action on the OC1x Register ...
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The timing diagram for the CTC mode is shown in (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then coun- ter (TCNT1) is cleared. Figure 14-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An ...
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In non-inverting compare output mode, the output compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x, and set at bottom. In inverting compare output mode, out- put is set on compare match and cleared at bottom. Due ...
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When changing the top value, the program must ensure that the new top value is higher or equal to the value of all of the compare registers. If the top value is lower than any of the com- pare registers, ...
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Phase Correct PWM Mode The phase correct pulse width modulation, or phase correct PWM, mode (WGM13 10, or 11) provides a high-resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like ...
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The timer/counter overflow flag (TOV1) is set each time the counter reaches bottom. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set accordingly on the same timer clock cycle on ...
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In inverting compare output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor ...
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When changing the top value, the program must ensure that the new top value is higher or equal to the value of all of the compare registers. If the top value is lower than any of the com- pare registers, ...
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Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling Figure 14-11 on page 111 Figure 14-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f Figure 14-12 on page 112 using phase and frequency correct PWM mode the OCR1x ...
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Figure 14-12. Timer/Counter Timing Diagram, no Prescaling Figure 14-13 on page 112 Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f Atmel ATtiny24/44/84 [Preliminary] 112 clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP ...
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Register Description 14.11.1 TCCR1A – Timer/Counter1 Control Register A Bit 0x2F (0x4F) Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 ...
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Table 14-3 correct or the phase and frequency correct, PWM mode. Table 14-3. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the count- ing sequence ...
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Table 14-4. Waveform Generation Mode Bit Description WGM12 Mode WGM13 (CTC1) (PWM11 ...
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When the ICR1 is used as top value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B registers), the ICP1 is disconnected, and, consequently, the input capture function is disabled. • Bit 5 – Reserved Bit ...
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A FOC1A/FOC1B strobe will not generate any interrupt, nor will it clear the timer in clear timer on compare match (CTC) mode using OCR1A as top. The FOC1A/FOC1B bits are always read as zero. • Bit 5..0 – Reserved Bit ...
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ICR1H and ICR1L – Input Capture Register 1 Bit 0x25 (0x45) 0x24 (0x44) Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the ...
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TIFR1 – Timer/Counter Interrupt Flag Register 1 Bit 0x0B (0x2B) Read/Write Initial Value • Bit 7,6,4,3 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to logical ...
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Timer/Counter Prescaler Timer/counter 0, and 1 share the same prescaler module, but the timer/counters can have dif- ferent prescaler settings. The description below applies to all timer/counters used as a general name, where ...
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Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (f uses sampling, the maximum ...
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USI – Universal Serial Interface 16.1 Features • Two-wire Synchronous Data Transfer (Master or Slave) • Three-wire Synchronous Data Transfer (Master or Slave) • Data Received Interrupt • Wakeup from Idle Mode • In Two-wire Mode: Wakeup from All ...
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The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the serial register and the counter are clocked simultaneously by the same clock source. This allows the counter to count ...
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Figure 16-3. Three-wire Mode, Timing Diagram CYCLE The Three-wire mode timing is shown in USCK cycle reference. One bit is shifted into the USI shift register (USIDR) for each of these cycles. The USCK timing is shown for both external ...
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SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: SPITransfer_loop: The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and ...
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SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (+ ret). The code example assumes that ...
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Two-wire Mode The USI two-wire mode is compliant with the Inter-IC (I2C or TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. Figure 16-4. ...
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Figure 16-5. Two-wire Mode, Typical Timing Diagram Referring to the timing diagram ing steps: 1. The start condition is generated by the Master by forcing the SDA line low while the SCL line is high (A). SDA can be forced ...
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Start Condition Detector The start condition detector is shown in the range 300ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in two-wire mode. The start condition detector is ...
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Register Descriptions 16.5.1 USIBR – USI Data Buffer Bit 0x10 (0x30) Read/Write Initial Value 16.5.2 USIDR – USI Data Register Bit 0x0F (0x2F) Read/Write Initial Value The USI uses no buffering for the serial register, i.e., when accessing the ...
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An interrupt will be generated when the flag is set while the USISIE bit in USICR and the global interrupt enable flag are set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing ...
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Bit 7 – USISIE: Start Condition Interrupt Enable Setting this bit to one enables the start condition detector interrupt. If there is a pending inter- rupt when the USISIE and the global interrupt enable flag are set to one, ...
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Bit 3..2 – USICS1..0: Clock Source Select These bits set the clock source for the shift register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data ...
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Analog Comparator The analog comparator compares the input values on the positive pin (AIN0) and negative pin (AIN1). When the voltage on the positive pin (AIN0) is higher than the voltage on the negative pin (AIN1), the analog comparator ...
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Table 17-1. ACME 17.2 Register Description 17.2.1 ADCSRB – ADC Control and Status Register B Bit 0x03 (0x23) Read/Write Initial Value • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logical one and the ADC ...
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Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit ...
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Analog-to-Digital Converter 18.1 Features • 10-bit Resolution • 1.0 LSB Integral Non-linearity • ±2 LSB Absolute Accuracy • 260µs Conversion Time • 76kSPS at Maximum Resolution • Eight Multiplexed Single-Ended Input Channels • Twelve differential ...
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Figure 18-1. Analog-to-Digital Converter Block Schematic ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 18.3 ADC Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approx- imation. The minimum value represents GND, and the ...
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If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input pair by the selected gain factor 20x, according to the setting of the MUX0 bit in the ADMUX register. This amplified ...
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Figure 18-2. ADC Auto Trigger Logic Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in free running mode, constantly sampling ...
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The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit ...
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Figure 18-6. ADC Timing Diagram, Auto Triggered Conversion Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL Figure 18-7. ADC Timing Diagram, Free Running Conversion Table 18-1. Condition First conversion Normal conversions Auto Triggered conversions Atmel ATtiny24/44/84 [Preliminary] 142 ...
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Changing Channel or Reference Selection The MUX5:0 and REFS1:0 bits in the ADMUX register are single-buffered through a tempo- rary register to which the CPU has random access. This ensures that the channel and reference selection only takes place ...
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ADC Noise Canceller The ADC features a noise canceller that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceller can be used with ADC noise reduction and idle ...
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Figure 18-8. Analog Input Circuitry 18.7.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying ...
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Gain Error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5LSB below maximum). Ideal value: 0LSB Figure 18-10. Gain Error • Integral ...
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Figure 18-12. Differential Non-linearity (DNL) • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1LSB wide) will code to the same value. Always ±0.5LSB. • Absolute Accuracy: ...
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The voltage of the positive pin must always be larger than the voltage of the negative pin or otherwise the voltage difference is saturated to zero. The result is presented in one-sided form, from 0x000 (0d) through 0x3FF (+1023d). The ...
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To obtain best accuracy the coefficient k should be measured using two temperature calibra- tions. Using offset calibration, set k = 1.0, where k = (1024*1.07mV/°C)/1.1V~1.0 [1/°C]. 18.10 Register Description 18.10.1 ADMUX – ADC Multiplexer Selection Register Bit 0x07 (0x27) ...
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Table 18-4. Notes: See Table 18-5 on page 151 selection of offset calibration channels. The MUX0 bit works as a gain selection bit for differen- tial channels, as shown in gain is selected, and when it is set (one) 20x ...
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Table 18-5. Positive Differential 1. 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Differential Input channel Selections. Negative Differential Input Input ADC0 (PA0) ADC0 (PA0) ADC1 (PA1) ADC3 (PA3) ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC0 ...
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ADCSRA – ADC Control and Status Register A Bit 0x06 (0x26) Read/Write Initial Value • Bit 7 – ADEN: ADC Enable Writing this bit to logical one enables the ADC. By writing it to zero, the ADC is turned ...
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Table 18-6. 18.10.3 ADCL and ADCH – ADC Data Register 18.10.3.1 ADLAR = 0 Bit 0x05 (0x25) 0x04 (0x24) Read/Write Initial Value 18.10.3.2 ADLAR = 1 Bit 0x05 (0x25) 0x04 (0x24) Read/Write Initial Value When an ADC conversion is complete, ...
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ADCSRB – ADC Control and Status Register B Bit 0x03 (0x23) Read/Write Initial Value • Bits 7 – BIN: Bipolar Input Mode The gain stage is working in the unipolar mode by default, but the bipolar mode can be ...
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Table 18-7. 18.10.5 DIDR0 – Digital Input Disable Register 0 Bit 0x01 (0x21) Read/Write Initial Value • Bits 7..0 – ADC7D..ADC0D: ADC7..0 Digital Input Disable When this bit is written logical one, the digital input buffer on the corresponding ADC ...
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On-chip Debug System 19.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for ...
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When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20k . However, the pull-up resistor is ...
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Self-Programming the Flash The device provides a self-programming mechanism (SPM) for downloading and uploading program code by the MCU itself. The self programming can use any available data interface and associated protocol to read code and write (program) that ...
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Performing a Page Write To execute a page write, set up the address in the Z-pointer, write "00000101" to SPMCSR, and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 are ignored. The ...
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EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to flash. Reading the fuses and lock bits from software will also be prevented during the EEPROM write opera- tion ...
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Flash corru ptio asily b e avoided by fo llowing at lea st one the se d esig n recommendations: 1. Keep the Atmel voltage. This can be done by enabling the internal Brown-out Detector (BOD) ...
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The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. ...
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Memory Programming This section describes the different methods for programming the Atmel memories. 21.1 Program And Data Memory Lock Bits The ATtiny24/44/84 provides two lock bits which can be left unprogrammed (set to one) or can be programmed (set ...
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Fuse Bytes The Atmel page 165 fuse bytes. Note that the fuses are read as logical zero ("0") if they are programmed. Table 21-3. Fuse High Byte SELFPRGEN Table 21-4. Fuse High Byte RSTDISBL DWEN SPIEN WDTON EESAVE BODLEVEL2 ...
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Table 21-5. Fuse Low Byte CKDIV8 CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes: The status of the fuse bits is not affected by chip erase. Note that the fuse bits are locked if lock bit 1 (LB1) is programmed. ...
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Page Size Table 21-7. Device ATtiny24 ATtiny44 ATtiny84 Table 21-8. Device ATtiny24 ATtiny44 ATtiny84 Atmel ATtiny24/44/84 [Preliminary] 166 No. of Words in a Page and No. of Pages in the Flash Flash Size Page Size PCWORD 1K words 16 ...
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Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set ...
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Serial Programming Algorithm When writing serial data to the Atmel edge of SCK. When reading data from the Atmel ATtiny24/44/84, data are clocked on the falling edge of SCK. See To program and verify the Atmel ATtiny24/44/84 in the ...
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Power-off sequence (if needed): Set RESET to “1”. Turn V Table 21-10. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol t WD_FLASH t WD_EEPROM t WD_ERASE t WD_FUSE 21.6.2 Serial Programming Instruction set Table 21-11 ...
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Table 21-11. Serial Programming Instruction Set (Continued) (1) Instruction/Operation Write Fuse bits Write Fuse High bits Write Extended Fuse Bits Notes: 1. Not all instructions are applicable for all parts. 2. adr = address 3. Bits are programmed ‘0’, unprogrammed ...
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High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the Atmel Figure 21-3. High-voltage Serial Programming Table 21-12. Pin Name Mapping Signal Name in High-voltage ...
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High-voltage Serial Programming Algorithm To program and verify the Atmel ming mode, the following sequence is recommended (see instruction formats in on page 21.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming ...
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Chip Erase The Chip Erase will erase the Flash and EEPROM bits are not reset until the program memory has been completely erased. The fuse bits are not changed. A chip erase must be performed before the flash and/or ...
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Figure 21-5. High-voltage Serial Programming Waveforms SDI MSB PB0 SII MSB PB1 SDO MSB PB2 SCI 0 1 PB3 21.8.5 Programming the EEPROM The EEPROM is organized in pages, see EEPROM, the data are latched into a page buffer. This ...
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Table 21-15. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx SDI 0_0001_0000_00 Load “Write Flash” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_ bbbb_bbbb _00 SII 0_0000_1100_00 SDO x_xxxx_xxxx_xx Load Flash Page ...
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Table 21-15. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 (Continued) Instruction Instr.1/5 SDI 0_bbbb_bbbb_00 SII 0_0000_1100_00 Write SDO x_xxxx_xxxx_xx EEPROM SDI 0_0000_0000_00 Byte SII 0_0110_0100_00 SDO x_xxxx_xxxx_xx SDI 0_0000_0011_00 Load “Read EEPROM” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_bbbb_bbbb_00 Read ...
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Note address high bits address low bits data in high bits data in low bits data out high bits data out low bits don’t care, 1 ...
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Electrical Characteristics 22.1 Absolute Maximum Ratings Automotive Operating Temperature ...............–40°C to +125°C Storage Temperature .....................................–65°C to +150°C Voltage on any Pin except RESET with respect to Ground ...............................–0. Voltage on RESET with respect to GND......... –0.5V to ...
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DC Characteristics Table 22-1. Symbol Parameter Power Supply Current I CC Power-down mode Analog Comparator Input I ACLK Leakage Current Notes: 1. All DC Characteristics contained in this data sheet are based on actual silicon characterization of Atmel ATtiny24/44/84 AVR ...
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Clock Characterizations 22.3.1 Calibrated Internal RC Oscillator Accuracy Table 22-2. Calibration Accuracy of Internal RC Oscillator Frequency Factory 8.0MHz Calibration User Calibration 7.3 - 8.1MHz Oscillator Jitter 8.0MHz Note: Example: with Oscillator divided by 32, jitter standard deviation will ...
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System and Reset Characterizations Table 22-4. Reset, Brown-out and Internal Voltage Reference Characteristics Symbol Parameter V Brown-out Detector Hysteresis HYST 2. V RAM Retention Voltage RAM t Min Pulse Width on Brown-out Reset BOD V Bandgap reference voltage BG ...
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ADC Characteristics – Preliminary Data Table 22-6. ADC Characteristics, Single Ended Channels. -40°C - 125°C Symbol Parameter Resolution Absolute accuracy (Including TUE INL, DNL, quantization error, gain and offset error) Integral Non-linearity (INL) INL Differential Non-linearity (DNL) DNL Gain ...
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Table 22-7. ADC Characteristics, Differential Channels, T Symbol Parameter Resolution TUE Absolute Accuracy INL Integral Non-Linearity (INL) DNL Differential Non-linearity (DNL) Gain Error 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] = -40°C to 125°C A Condition Min Gain = 1x Gain = 20x ...
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Table 22-7. ADC Characteristics, Differential Channels, T Symbol Parameter Offset Error Clock Frequency Conversion Time V Reference Voltage REF V Input Voltage IN V Input Differential Voltage DIFF 22.6 Serial Programming Characteristics Figure 22-3. Serial Programming Timing Figure 22-4. Serial ...
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Table 22-8. Symbol 1/t t CLCL 1/t t CLCL t SHSL t SLSH t OVSH t SHOX t SLIV Note: 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] Serial Programming Characteristics, T (Unless Otherwise Noted) Parameter Oscillator Frequency (Atmel ATtiny24/44/84V) CLCL Oscillator Period (Atmel ...
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High-voltage Serial Programming Characteristics Figure 22-5. High-voltage Serial Programming Timing Table 22-9. Symbol WLWH_PFB Atmel ATtiny24/44/84 [Preliminary] 186 CC CK High-voltage Serial Programming Characteristics T = 25°C ± 10 5.0V ± 10% (Unless ...
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Typical Characteristics – Preliminary Data The data contained in this section is largely based on simulations and characterization of sim- ilar devices in the same process and design methods. Thus, the data should be treated as indications of how ...
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Figure 23-2. Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) - Temp.=125°C Figure 23-3. Active Supply Current vs. frequency (1 - 20MHz) - Temp.=25°C Atmel ATtiny24/44/84 [Preliminary] 188 ACTIVE CURRENT vs . LOW FREQUENCY 0.1 ...
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Figure 23-4. Active Supply Current vs. frequency (1 - 20MHz) - Temp.=125°C Figure 23-5. Active Supply Current vs. V 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] ACTIVE CURRENT vs . FREQUENCY MHz - Temperature = 125˚C ...
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Figure 23-6. Active Supply Current vs. V Figure 23-7. Active Supply Current vs. V Atmel ATtiny24/44/84 [Preliminary] 190 ACTIVE CURRENT INTERNAL RC OSCILLATOR, 1MHz 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2.5 ...
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Idle Supply Current Figure 23-8. Idle Supply Current vs. Low Frequency (0.1 - 1.0MHz) Figure 23-9. Idle Supply Current vs. Frequency (1 - 20MHz) 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] IDLE CURRENT vs . LOW FREQUENCY 0.1 ...
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Figure 23-10. Idle Supply Current vs. V Figure 23-11. Idle Supply Current vs. V Atmel ATtiny24/44/84 [Preliminary] 192 CC IDLE CURRENT INTERNAL RC OSCILLATOR, 8 MHz 2 1.8 1.6 1.4 1.2 1 0.8 ...
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Figure 23-12. Idle Supply Current vs. V 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] CC IDLE CURRENT INTERNAL RC OSCILLATOR, 128 KHz 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 2.5 3 3.5 (Internal RC Oscillator, ...
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Supply Current of IO modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled ...
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Figure 23-14. Power-down Supply Current vs. V 23.5 Pin Pull-up Figure 23-15. I/O Pin Pull-up Resistor Current vs. input Voltage (V 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] P OWER-DOWN CURRENT WATCHDOG TIMER ENABLED 10 9 ...
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Figure 23-16. I/O pin Pull-up Resistor Current vs. Input Voltage (V Figure 23-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V Atmel ATtiny24/44/84 [Preliminary] 196 I ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE ...
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Figure 23-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 23.6 Pin Driver Strength Figure 23-19. I/O Pin Output Voltage vs. Sink Current (V 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] RES ET P ULL-UP RES IS TOR CURRENT vs . RES ...
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Figure 23-20. I/O pin Output Voltage vs. Sink Current (V Figure 23-21. I/O Pin Output Voltage vs. Source Current (V Atmel ATtiny24/44/84 [Preliminary] 198 I OUTP UT VOLTAGE INK CURRENT LOW POWER PINS - Vcc ...
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Figure 23-22. I/O Pin output Voltage vs. Source Current (V 23.7 Pin Threshold and Hysteresis Figure 23-23. I/O Pin Input Threshold Voltage vs. V 7701E–AVR–02/11 Atmel ATtiny24/44/84 [Preliminary] I OUTP UT VOLTAGE OURCE CURRENT LOW ...
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Figure 23-24. I/O Pin Input threshold Voltage vs. V Figure 23-25. I/O Pin Input Hysteresis vs. V Atmel ATtiny24/44/84 [Preliminary] 200 I INP UT THRES HOLD VOLTAGE VIL, IO PIN READ AS '0' 2.5 2 ...