ATtiny461 Automotive Atmel Corporation, ATtiny461 Automotive Datasheet - Page 26

• Manufacturer Part Number: ATtiny461 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny461 Automotive

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7.1.5
26
ATtiny261/ATtiny461/ATtiny861
Internal PLL for Fast Peripheral Clock Generation - clk
The internal PLL in ATtiny261/461/861 generates a clock frequency that is 8x multiplied from a
source input. By default, the PLL uses the output of the internal 8.0 MHz RC oscillator as source.
Alternatively, if the LSM bit of the PLLCSR is set the PLL will use the output of the RC oscillator
divided by two. Thus the output of the PLL, the fast peripheral clock is 64 MHz. The fast periph-
eral clock, or a clock prescaled from that, can be selected as the clock source for
Timer/Counter1or as a system clock. See
is divided by two when LSM of PLLCSR is set, resulting in a clock frequency of 32 MHz. Note,
that LSM can not be set if PLL
Figure 7-2.
The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will
adjust the fast peripheral clock at the same time. However, even if the RC oscillator is taken to a
higher frequency than 8 MHz, the fast peripheral clock frequency saturates at 85 MHz (worst
case) and remains oscillating at the maximum frequency. It should be noted that the PLL in this
case is not locked any longer with the RC oscillator clock. Therefore, it is recommended not to
take the OSCCAL adjustments to a higher frequency than 8 MHz in order to keep the PLL in the
correct operating range.
The internal PLL is enabled when:
• The PLLE bit of the PLLCSR register is set.
• The CKSEL fuse are programmed to ‘0001’.
The PLLCSR bit PLOCK is set when PLL is locked.
Both internal RC oscillator and PLL are switched off in power down and stand-by sleep modes.
XTAL1
XTAL2
OSCCAL
OSCILLATORS
OSCILLATOR
8.0 MHz
PCK Clocking System
LSM
1/2
CLK
4 MHz
8 MHz
is used as a system clock.
PCK
Figure
PLLE
PLL
8x
7-2. The frequency of the fast peripheral clock
64 / 32 MHz
DETECTOR
1/4
LOCK
16 MHz
8 MHz
CKSEL3:0
PRESCALER
CLKPS3:0
7753F–AVR–01/11
SYSTEM
PLOCK
CLOCK
PCK