ATmega162 Atmel Corporation, ATmega162 Datasheet - Page 98

• Manufacturer Part Number: ATmega162
• Manufacturer: Atmel Corporation

Specifications of ATmega162

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 6
• Input Capture Channels: 2
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Timer/Counter
Timing Diagrams
98
ATmega162/V
The extreme values for the OCR0 Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the out-
put will be continuously low and if set equal to MAX the output will be continuously high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM.
There are two cases that give a transition without Compare Match.
•
•
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 40. Timer/Counter Timing Diagram, no Prescaling
Figure 41
Figure 41. Timer/Counter Timing Diagram, with Prescaler (f
Figure 42
OCR0 changes its value from MAX, like in
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
The timer starts counting from a value higher than the one in OCR0, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
TCNTn
(clk
TCNTn
(clk
TOVn
TOVn
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/8)
/1)
shows the same timing data, but with the prescaler enabled.
shows the setting of OCF0 in all modes except CTC mode.
Figure 40
MAX - 1
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
Figure 39
OCn has a transition from high to low even though there
MAX
MAX
Figure
39. When the OCR0 value is MAX the
clk_I/O
BOTTOM
BOTTOM
/8)
T
0) is therefore shown as a
BOTTOM + 1
BOTTOM + 1
2513K–AVR–07/09