ATmega162 Atmel Corporation, ATmega162 Datasheet - Page 94

• Manufacturer Part Number: ATmega162
• Manufacturer: Atmel Corporation

Specifications of ATmega162

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 6
• Input Capture Channels: 2
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Compare Output Mode
and Waveform
Generation
Modes of
Operation
Normal Mode
Clear Timer on
Compare Match (CTC)
Mode
94
ATmega162/V
The design of the output compare pin logic allows initialization of the OC0 state before the out-
put is enabled. Note that some COM01:0 bit settings are reserved for certain modes of
operation.
The Waveform Generator uses the COM01:0 bits differently in Normal, CTC, and PWM modes.
For all modes, setting the COM01:0 = 0 tells the Waveform Generator that no action on the OC0
Register is to be performed on the next Compare Match. For Compare Output actions in the
non-PWM modes refer to
101, and for phase correct PWM refer to
A change of the COM01:0 bits state will have effect at the first Compare Match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC0 strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output
mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM01:0 bits control whether the PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM01:0 bits control whether the output should be set, cleared, or toggled at a Compare
Match
For detailed timing information refer to
“Timer/Counter Timing Diagrams” on page
The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same
timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The output compare unit can be used to generate interrupts at some given time. Using the out-
put compare to generate waveforms in Normal mode is not recommended, since this will occupy
too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to manip-
ulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value
(TCNT0) matches the OCR0. The OCR0 defines the top value for the counter, hence also its
resolution. This mode allows greater control of the Compare Match output frequency. It also sim-
plifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
increases until a Compare Match occurs between TCNT0 and OCR0, and then counter (TCNT0)
is cleared.
(See “Compare Match Output Unit” on page
See “8-bit Timer/Counter Register Description” on page 100.
Table 48 on page
Table 50 on page
Figure
98.
101. For fast PWM mode, refer to
40,
93.).
Figure
Figure
101.
37. The counter value (TCNT0)
41,
Figure 42
and
Table 49 on page
2513K–AVR–07/09
Figure 43
in