ATmega162 Atmel Corporation, ATmega162 Datasheet - Page 30

• Manufacturer Part Number: ATmega162
• Manufacturer: Atmel Corporation

Specifications of ATmega162

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 6
• Input Capture Channels: 2
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

XMEM Register
Description
MCU Control Register
– MCUCR
Extended MCU
Control Register –
EMCUCR
30
ATmega162/V
Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1
Note:
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,
ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin
direction settings in the respective Data Direction Registers. Writing SRE to zero, disables the
External Memory Interface and the normal pin and data direction settings are used.
• Bit 6 – SRW10: Wait State Select Bit
For a detailed description, see common description for the SRWn bits below (EMCUCR
description).
• Bit 6..4 – SRL2, SRL1, SRL0: Wait State Sector Limit
It is possible to configure different wait-states for different external memory addresses. The
external memory address space can be divided in two sectors that have separate wait-state bits.
The SRL2, SRL1, and SRL0 bits select the splitting of these sectors, see
By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory
address space is treated as one sector. When the entire SRAM address space is configured as
one sector, the wait-states are configured by the SRW11 and SRW10 bits.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
System Clock (CLK
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal
or external).
SRE
SM0
DA7:0
R/W
R/W
A15:8
CPU
ALE
WR
7
0
7
0
RD
)
Prev. addr.
Prev. data
Prev. data
SRW10
SRL2
R/W
R/W
6
0
6
0
T1
SRL1
Address
R/W
R/W
Address
SE
5
0
5
0
Address
T2
XX
SRL0
SM1
R/W
R/W
4
0
4
0
Address
T3
Data
Data
Data
SRW01
ISC11
R/W
R/W
3
0
3
0
T4
SRW00
ISC10
R/W
R/W
2
0
2
0
T5
SRW11
ISC01
R/W
R/W
1
0
1
0
T6
ISC00
ISC2
R/W
R/W
Table 2
0
0
0
0
(1)
EMCUCR
T7
MCUCR
and
2513K–AVR–07/09
Figure
11.