ATmega162 Atmel Corporation, ATmega162 Datasheet - Page 51

• Manufacturer Part Number: ATmega162
• Manufacturer: Atmel Corporation

Specifications of ATmega162

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 6
• Input Capture Channels: 2
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Watchdog Reset
MCU Control and
Status Register –
MCUCSR
2513K–AVR–07/09
Figure 25. Brown-out Reset During Operation
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
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Figure 26. Watchdog Reset During Operation
The MCU Control and Status Register provides information on which reset source caused an
MCU Reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
Bit
Read/Write
Initial Value
INTERNAL
TIME-OUT
for details on operation of the Watchdog Timer.
RESET
RESET
CC
V
CC
R/W
JTD
7
0
R/W
6
–
0
SM2
R
5
0
V
BOT-
JTRF
CK
R/W
4
WDRF
R/W
3
See Bit Description
BORF
R/W
2
EXTRF
R/W
V
t
1
TOUT
BOT+
ATmega162/V
PORF
R/W
0
MCUCSR
TOUT
. Refer to
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