ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 35

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.6.6
8151H–AVR–02/11
XMCRB - External Memory Control Register B
Table 7-4.
Note:
• Bit 0 – Res: Reserved Bit
This is a reserved bit and will always read as zero. When writing to this address location, write
this bit to zero for compatibility with future devices.
• Bit 7– XMBK: External Memory Bus-keeper Enable
Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is
enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise
be tri-stated. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so
even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is
one.
• Bit 6:4 – Reserved
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bit 2:0 – XMM2, XMM1, XMM0: External Memory High Mask
When the External Memory is enabled, all Port C pins are default used for the high address byte.
If the full 60Kbytes address space is not required to access the External Memory, some, or all,
Port C pins can be released for normal Port Pin function as described in
in
XMMn bits to access all 64Kbytes locations of the External Memory.
Table 7-5.
Bit
Read/Write
Initial Value
SRWn1
XMM2
“Using all 64 Kbytes Locations of External Memory” on page
0
0
0
0
0
0
1
1
1. n = 0 or 1 (lower/upper sector).
For further details of the timing and wait-states of the External Memory Interface, see Figures
7-6 through Figures 7-9 for how the setting of the SRW bits affects the timing.
XMM1
SRWn0
0
0
1
1
Wait States
Port C Pins Released as Normal Port Pins when the External Memory is Enabled
XMBK
0
1
0
1
R/W
7
0
XMM0
Wait States
No wait-states
Wait one cycle during read/write strobe
Wait two cycles during read/write strobe
Wait two cycles during read/write and wait one cycle before driving out new
address
0
1
0
1
(1)
R
6
–
0
# Bits for External Memory Address
8 (Full 60 Kbytes space)
7
6
5
R
5
–
0
R
4
–
0
R
3
–
0
XMM2
R/W
2
0
28, it is possible to use the
XMM1
ATmega128A
R/W
1
0
Table
Released Port Pins
None
PC7
PC7 - PC6
PC7 - PC5
7-5. As described
XMM0
R/W
0
0
XMCRB
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