ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 153

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.6.1
17.7
17.7.1
17.7.2
8151H–AVR–02/11
Modes of Operation
Compare Output Mode and Waveform Generation
Normal Mode
Clear Timer on Compare Match (CTC) Mode
The waveform generator uses the COM21:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COM21:0 = 0 tells the waveform generator that no action on the OC2
Register is to be performed on the next compare match. For compare output actions in the non-
PWM modes refer to
160, and for phase correct PWM refer to
A change of the COM21:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC2 strobe bits.
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Out-
put mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM21:0 bits control whether the PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM21:0 bits control whether the output should be set, cleared, or toggled at a compare
match (see “Compare Match Output Unit” on page 152).
For detailed timing information refer to
in
The simplest mode of operation is the normal mode (WGM21:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter overflow flag (
timer clock cycle as the TCNT2 becomes zero. The
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the
are no special cases to consider in the normal mode, a new counter value can be written
anytime.
The output compare unit can be used to generate interrupts at some given time. Using the out-
put compare to generate waveforms in normal mode is not recommended, since this will occupy
too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manip-
ulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value
(TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its
resolution. This mode allows greater control of the compare match output frequency. It also sim-
plifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
increases until a compare match occurs between TCNT2 and OCR2 and then counter (TCNT2)
is cleared.
“Timer/Counter Timing Diagrams” on page
Table 17-3 on page
TOV
2 flag, the timer resolution can be increased by software. There
Figure
Table 17-5 on page
160. For fast PWM mode, refer to
157.
17-8,
Figure
TOV
Figure
2 flag in this case behaves like a ninth
17-9,
17-5. The counter value (TCNT2)
161.
Figure
TOV
ATmega128A
2) will be set in the same
17-10, and
Table 17-4 on page
Figure 17-11
153