ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 192

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.8.1
20.9
20.9.1
8151H–AVR–02/11
Register Description
Using MPCM
UDRn - USARTn I/O Data Register
data bits, then the ninth bit (RXB8) is used for identifying address and data frames. When the
frame type bit (the first stop or the 9th bit) is one, the frame contains an address. When the
frame type bit is zero the frame is a data frame.
The Multi-processor Communication mode enables several slave MCUs to receive data from a
master MCU. This is done by first decoding an address frame to find out which MCU has been
addressed. If a particular slave MCU has been addressed, it will receive the following data
frames as normal, while the other slave MCUs will ignore the received frames until another
address frame is received.
For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ = 7). The
ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or cleared when a data frame
(TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character
frame format.
The following procedure should be used to exchange data in Multi-processor Communication
mode:
Using any of the 5-bit to 8-bit character frame formats is possible, but impractical since the
receiver must change between using n and n+1 character frame formats. This makes full-duplex
operation difficult since the transmitter and receiver uses the same character size setting. If 5-bit
to 8-bit character frames are used, the transmitter must be set to use two stop bit (USBS = 1)
since the first stop bit is used for indicating the frame type.
Do not use read-modify-write instructions (SBI and CBI) to set or clear the MPCM bit. The
MPCM bit shares the same I/O location as the TXC flag and this might accidentally be cleared
when using SBI or CBI instructions.
The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Registers share
the same I/O address referred to as USARTn Data Register or UDRn. The Transmit Data Buffer
Bit
Read/Write
Initial Value
1. All slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA is set).
2. The master MCU sends an address frame, and all slaves receive and read this frame.
3. Each slave MCU reads the UDR Register and determines if it has been selected. If so,
4. The addressed MCU will receive all data frames until a new address frame is received.
5. When the last data frame is received by the addressed MCU, the addressed MCU sets
In the slave MCUs, the RXC flag in UCSRA will be set as normal.
it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte and
keeps the MPCM setting.
The other slave MCUs, which still have the MPCM bit set, will ignore the data frames.
the MPCM bit and waits for a new address frame from master. The process then
repeats from 2.
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
RXBn[7:0]
TXBn[7:0]
R/W
3
0
R/W
2
0
R/W
1
0
ATmega128A
R/W
0
0
UDRn (Write)
UDRn (Read)
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