ATmega128A Atmel Corporation, ATmega128A Datasheet - Page 137

• Manufacturer Part Number: ATmega128A
• Manufacturer: Atmel Corporation

Specifications of ATmega128A

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 15-5.
Note:
15.11.3
15.11.4
8151H–AVR–02/11
Mode
12
13
14
15
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the
WGMn3
TCCR1B - Timer/Counter1 Control Register B
TCCR3B - Timer/Counter3 Control Register B
location of these bits are compatible with previous versions of the timer.
1
1
1
1
Waveform Generation Mode Bit Description
WGMn2
(CTCn)
1
1
1
1
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is
activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture
event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the
TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCRnB is written.
• Bit 4:3 – WGMn3:2: Waveform Generation Mode
See TCCRnA Register description.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(PWMn1)
WGMn1
0
0
1
1
ICNC1
ICNC3
(PWMn0)
R/W
R/W
WGMn0
7
0
7
0
0
1
0
1
ICES1
ICES3
R/W
R/W
6
0
6
0
CTC
(Reserved)
Fast PWM
Fast PWM
Timer/Counter Mode of
R
R
5
–
0
5
–
0
Operation
WGM33
WGM13
R/W
R/W
4
0
4
0
(1)
WGM
WGM12
WGM32
n2:0 definitions. However, the functionality and
R/W
R/W
3
0
3
0
ICRn
–
ICRn
OCRnA
TOP
CS32
CS12
R/W
R/W
2
0
2
0
Immediate
–
BOTTOM
BOTTOM
OCRn
Update of
CS31
CS11
ATmega128A
R/W
R/W
1
0
1
0
x
at
CS30
CS10
R/W
R/W
0
0
0
0
MAX
–
TOP
TOP
TOVn Flag
Set on
TCCR3B
TCCR1B
137