SC28L202A1DGG/G,11 NXP Semiconductors, SC28L202A1DGG/G,11 Datasheet - Page 27

• Manufacturer Part Number: SC28L202A1DGG/G,11
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG/G,11

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279792118; SC28L202A1DGG/G-T; SC28L202A1DGG/G-T

Philips Semiconductors
MR1 – Mode Register 1, A and B
MR1 can be accessed directly at H’21’ and H’29’ in the Extended section of the address map, or by means of the ‘MR Pointers’ at the 0x00 and
0x08 address pointers used by legacy code.
MR1[7] – Receiver Request to Send (hardware flow control)
This bit controls the deactivation of the RTSN output (I/O2) by the
receiver. The I/O2 output is asserted and negated by commands
applied via the command register or through the setting of the OPR
register bits. MR1[7] = 1 enables the receiver state machine to
controls the sate of the I/O2 (where the RTSN function is assigned)
to be automatically negated (driven high) upon receipt of a valid start
bit if the receiver FIFO is 240 full or greater. (for 8-byte mode the
FIFO full signal is used) RTSN is reasserted when the FIFO fill level
falls below 240 filled FIFO positions. This constitutes a change from
previous members of Philips (Signets)’ UART families where the
RTSN function triggered on FIFO full. This behavior caused
problems with PC UARTs that could not stop transmission at the
proper time.
NOTE: When the FIFO is set to an 8-byte depth the RTSN signaling
is triggered on position 8 of the FIFO
The RTSN feature can be used to prevent overrun in the receiver, by
using the RTSN output signal, to control the CTSN (see MR2(4)
description) input of the transmitting device. It is not recommend to
use the hardware flow control and the ‘in-band’ (Xon/Xoff) flow
control at the same time although the DUART hardware will allow it.
To use the RTSN function:
1. Set MR1(7) to 1
2. Set I/O0 B or I/O1 B as appropriate to logical 0
3. Enable receiver
MR1[6] – Receiver interrupt control bit 1.
See description under MR0 [6]. (Writing to this register will reset the
RxFIFO interrupt to the bit configuration of MR0 and MR1. Reading
has no effect.)
*** change in MR in legacy section – at MR0 also***
2005 Nov 01
Dual UART
Bit 7
RxRTS Control
0 = off
1 = on
Bit 6
See Tables in MR0
description
Bit 5
Error Mode
0 = Character
1 = Block
(entry or exit)
21
Bit 4:3
Parity Mode
00 = With Parity
01 = Force parity
10 = No parity
11 = Multi drop Special Mode
MR1 [5] – Error Mode Select and sub modes
This bit selects the operating mode of the three FIFOed status bits
(FE, PE, and received break). In the character mode, status is
provided on a character by character basis; the status applies only
to the character at the output of the FIFO.
In the block mode, the status provided in the SR for these bits is the
accumulation (logical OR) of the status for all characters coming to
the output of the FIFO, since the last reset error command was
issued.
The Block Error mode has two-sub mode. These modes are
controlled by the command register. The error is ‘accumulated’ (as
described above) at either the entry of the data in to the FIFO or on
the exit (read of the FIFO). Of the two the setting of the error on the
entry of the data into the FIFO gives the earliest warning of error
data.
MR1[4:3] – Parity Mode Select
If ’with parity’ or ’force parity’ is selected, a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data. MR1[4:3] = 11 selects the channel to operate in the
special wake up mode.
MR1[2] – Parity Type Select
This bit sets the parity type (odd or even) if the ’with parity’ mode is
programmed by MR1[4:3], and the polarity of the forced parity bit if
the ’force parity’ mode is programmed it has no effect if the ’no
parity’ mode is programmed. In the special ’wake up’ mode, it
selects the polarity of the A/D bit. The parity bit is used to an
address or data byte in the ’wake up’ mode.
MR1[1:0] – Bits per Character Select
This field selects the number of data bits per character to be
transmitted and received. This number does not include the start,
parity, or stop bits.
Bit 2
Parity Type
0 = Even
1 = Odd
SC28L202
Bit 1:0
Bits per
Character
00 = 5
01 = 6
10 = 7
11 = 8
Product data sheet