SC28L202A1DGG/G,11 NXP Semiconductors, SC28L202A1DGG/G,11 Datasheet - Page 16

• Manufacturer Part Number: SC28L202A1DGG/G,11
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG/G,11

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279792118; SC28L202A1DGG/G-T; SC28L202A1DGG/G-T

Philips Semiconductors
the receiver operates as if a new start bit had been detected. It then
continues assembling the next character.
The error conditions of parity error, framing error, and overrun error
(if any) are written to the SR at the received character boundary.
This is just before the RxRDY status bit is set.
A break condition is detected when RxD is Low for the entire
character including the parity bit, if used, and stop bit. When a break
is found a character consisting of all zeros will be loaded into the
RxFIFO, the received break bit in the SR and the ‘change of break’
bit in the ISR are set to 1 and the receiver ready is set in the SR.
The RxD input must return to high for two (2) clock edges of the
RxC1x clock for the receiver to recognize the end of the break
condition. At the end of the break condition the search for the next
start bit begins.
Two edges of the RxC1x clock will usually require a high time of one
RxC1x clock period or 3 RxC1x edges since the clock of the
controller is usually not synchronous to nor in phase with the RxC1x
clock.
Receiver Status Bits
There are five (5) status bits that are evaluated with each byte (or
character) received: received break, framing error, parity error,
overrun error, and change of break. The first three are appended to
each byte and stored in the RxFIFO. The last two are not
necessarily related to the byte being received or a byte that is in the
RxFIFO. They are however developed by the receiver state
machine.
The receiver status bits are normally cleared by servicing the
interrupt condition they represent or by Rx reset or Rx disable
commands or the several error reset commands in the Command
Register (CR).
The ‘received break’ will always be associated with a zero byte in
the RxFIFO. It means that zero character was a break character and
not a zero data byte. The reception of a break condition will always
set the ‘change of break’ (see below) status bit in the Interrupt
Status Register (ISR).
The Change of break condition is reset by a reset error status
command in the command register
A framing error occurs when a non-zero character was seen and
that character has a zero in the stop bit position.
The parity error indicates that the receiver-generated parity was not
the same as that sent by the transmitter.
The framing, parity and received break status bits are reset when
the associated data byte is read from the RxFIFO since these ‘error’
conditions are attached to the byte that has the error
The overrun error occurs when the RxFIFO is full, the receiver shift
register is full, and another start bit is detected. At this moment the
receiver has 257 valid characters and the start bit of the 258
been seen. At this point the host has approximately 6/16 bit time to
read a byte from the RxFIFO or the overrun condition will be set.
The 258
and so on until an open position in the RxFIFO is seen. (‘seen’
meaning at least one byte was read from the RxFIFO.)
Overrun is cleared by a use of the ‘error reset’ command in the
command register.
The fundamental meaning of the overrun is that data has been lost.
Data in the RxFIFO remains valid. The receiver will begin placing
characters in the RxFIFO as soon as a position becomes vacant.
2005 Nov 01
Dual UART
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character then overruns the 257
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and the 258
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the 259
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has
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NOTE: Precaution must be taken when reading an overrun FIFO.
There will be 256
be one character in the receiver shift register. However it will NOT
be known if more than one ‘over-running’ character has been
received since the overrun bit was set. The 257
and read as valid but it will not be known how many characters were
lost between the two characters of the 256
RxFIFO. In the 8-bit mode, the numbers 8 and 9 replace the
numbers 256 and 257 above.
The ‘Change of break’ means that either a break has been detected
or that the break condition has been cleared. This bit is available in
the ISR. The break change bit being set in the ISR and the received
break bit being set in the SR will signal the beginning of a break. At
the termination of the break condition only the change of break in
the ISR will be set. After the break condition is detected the
termination of the break will only be recognized when the RxD input
has returned to the high state for two successive edges of the 1x
clock; 1/2 to 1 bit time. (see above)
The receiver is disabled by reset or via CR commands. A disabled
receiver will not interrupt the host CPU under any circumstance in
the normal mode of operation. If the receiver is in the multi-drop or
special mode, it will be partially enabled and thus may cause an
interrupt. Refer to section on Wake-Up and the register description
for MR1 for more information.
Receiver FIFO
The receiver buffer memory is a 256 byte FIFO with three status bits
appended to each data byte. (The FIFO is then 256 11-bit ‘words’).
The receiver state machine gathers the bits from the receiver shift
register and the status bits from the receiver logic and writes the
assembled byte and status bits to the RxFIFO shortly after the stop
bit has been sampled. Logic associated with the FIFO encodes the
number of filled positions for presentation to the interrupt arbitration
system. The encoding is always the number of filled positions. Thus,
a full RxFIFO will bid with the value of 255 and the Status Register
RxFULL bit is set. When empty it will not bit at all. One position
occupied bids with the value 1. An empty FIFO will not bid since no
character is available.
Normally RxFIFO will present a bid to the arbitration system
whenever it has one or more filled positions. The bits of the RxFIFO
Interrupt Offset Level (RxFIL) or the bits of the MR2(3:2) allow the
user to modify this characteristic so that bidding will not start until
one of four levels (one or more filled, 64 filled, 192 filled, full) have
been reached. As will be shown later this feature may be used to
make slight improvements in the interrupt service efficiency. A
similar system exists in the transmitter.
RxFIFO Status Bits. Status reporting modes
This description applies to the upper three bits in the ‘Status
Register’. These three bits are not ‘in the status register’; they are
part of the RxFIFO. The three status bits at the output of the RxFIFO
are presented as the upper three bits of the status register included
in each UART.
The error status of a character, as reported by a read of the SR
(status register upper three bits) can be provided in two ways, as
programmed by the error mode control bit in the mode register:
‘Character mode’ or the ‘Block Mode’. The block mode may be
further modified (via a CR command) to set the status bits as the
characters enter the FIFO or as they are read from the FIFO.
In the ‘character’ mode, status is provided on a character by
character basis as the characters are read from the RxFIFO: the
‘status’ applies only to the character at the output of the
RxFIFO—The next character to be read.
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valid characters in the receiver FIFO. There will
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and 257
SC28L202
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character received
Product data sheet
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reads of the