SC28L202A1DGG/G,11 NXP Semiconductors, SC28L202A1DGG/G,11 Datasheet - Page 17

• Manufacturer Part Number: SC28L202A1DGG/G,11
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG/G,11

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279792118; SC28L202A1DGG/G-T; SC28L202A1DGG/G-T

Philips Semiconductors
In the ‘block’ mode (on entry) the status provided in the SR for these
three bits is the logical OR of the status for all characters coming to
the input of the RxFIFO since the last reset error command was
issued. In this mode each of the status bits stored in the RxFIFO are
passed through a latch as they are sequentially written to the
receiver FIFO. If any of the characters has an error bit set that latch
will set and remain set until it is reset with a ‘receiver reset’ issued
from the command register or a chip reset is issued. The purpose of
this mode is indicating an error in the data block as opposed to an
error in a character. This mode improves receiver service efficiency.
In modern systems with low error rates, it is more efficient to ask for
retransmit of a block error data than to analyze it on a byte by byte
system.
The above paragraph describes the block mode activity as the data
is entered to the RxFIFO. Normally the status would be read only
once—at the beginning of the service to the receiver interrupt. If an
error is not set then the entire amount of data in the RxFIFO would
be read without any more reading if the receiver status. This
effectively doubles the efficiency of reading the receiver RxFIFO.
The use of the block mode on Exit passes the data and error
conditions as the RxFIFO is read. Here the final read of the status
register would be after the last byte was read from the RxFIFO. This
delays the knowledge of an error condition until after the data has
been read.
The latch used in the block mode to indicate ‘problem data’ is
usually set as the characters are read out of the RxFIFO. Via a
command in the CR the latch may be configured to set as error
characters are loaded to the RxFIFO. This gives the advantage of
indicating ‘problem data’ up to 256 (or the FIFO size) characters
earlier.
In either mode, reading the SR does not affect the RxFIFO. The
RxFIFO address is advanced only when the RxFIFO is read.
Therefore, the SR should be read prior to reading the corresponding
data character.
If the RxFIFO is full when a new character is received, the character
is held in the receiver shift register until a position is available in the
RxFIFO. At this time there are 257 valid characters in the RxFIFO. If
an additional character is received while this state exists, the
contents of the RxFIFO are not affected: the character previously in
the shift register is lost and the overrun error status bit, SR [4], will
be set upon receipt of the start bit of the new (overrunning)
character.
Wake Up Mode (Also the ‘9-bit’, ‘multi-drop’, ‘party; line’ or Special
mode)
The SC28L202 provides four modes of this common asynchronous
‘party line’ protocol where the parity bit is used to indicate that a byte
is address data or information data. Three automatic modes and the
default Host operated mode are provided. The automatic mode has
several sub modes (see below). In the full automatic the internal
state machine devoted to this function will handle all operations
associated with address recognition, data handling, receiver enables
and disables. In both modes the meaning of the parity bit is
changed. It is often referred to as the A/D bit or the address/data
bit—sometimes the ‘9th’ bit. It is used to indicate whether the byte
presently in the receiver shift register is an ‘address’ byte or a ‘data’
byte. A ‘1’ usually means address, a ‘0’ data.
Its purpose is to allow several receivers connected to the same data
source to be individually addressed. Of course addressing could be
by group also. Normally the ‘Master’ would send an address byte to
all receivers ‘listening’. The remote receiver will be ‘looking’ at the
data stream for its address. Upon recognition of its address it will
2005 Nov 01
Dual UART
11
enable itself to receive the following data stream. Upon receipt of an
address not its own it would then disable itself. As descried below
appropriate status bits are available to describe the operation.
Again, for this mode an ‘address byte’ is a byte that has the bit in the
parity position set to logical 1.
The use of the multi-drop mode usually implies a ‘master and slave’
configuration of the several UART stations so programmed. The
software control should allow time for the slave stations to respond
to the receipt of an address bit. Often a reply from the addressed
station is expected to confirm the receipt of the address. Please see
control the automatic features of the address recognition in
MR3[1:0].
Enabling the Wake Up mode
(This mode is variously referred to as ‘9-bit’ or ‘Multi-drop’.)
This mode is selected by programming bits MR1 [4:3] (the parity
bits) to ’11’. The wake up feature has four modes of operation: one
strictly under processor control and three automatic. These modes
are controlled by bits 6, 1, 0 in the MR3 register. Bit 6 controls the
loading of the address byte to the RxFIFO and MR3[1:0] determines
the sub mode as shown in the following list.
MR3[1:0] = 00 Normal Wake Up Mode (default) which is the same
as previous DUARTs and is therefore controlled by the processor.
The Host controls operation via interrupts it receives and commands
it writes to the DUART command registers (CR).
Normal Wake up (The default configuration)
The enabling of the wake-up mode executes a partial enabling of the
receiver state machine. Even though the receiver has been reset the
wake up mode will over ride the disable and reset condition.
In the default (mode ‘00’ above and the least efficient) configuration
for this mode of operation, a ’master’ station transmits an address
character followed by data characters for the addressed ’slave’
station. The slave stations, whose receivers are normally disabled
(not reset), examine the received data stream. Upon recognition of
its address bit (this is the parity bit redefined to indicate the
associated byte is an address bye – not the address itself)
interrupts the CPU (by setting RxRDY). The CPU (host) compares
the received address to its station address and enables the receiver
if it wishes to receive the subsequent data characters. Upon receipt
of another address character, the CPU may disable the receiver to
initiate the process again.
A transmitted character consists of a start bit; the programmed
number of data bits, an address/data (A/D) bit and the programmed
number of stop bits. The CPU selects the polarity of the transmitted
A/D bit by programming bit MR1 [2]. MR1 [2] = 0 transmits a zero in
the A/D bit position which identifies the corresponding data bits as
data. MR1 [2] = 1 transmits a one in the A/D bit position which
identifies the corresponding data bits as an address. The CPU
should program the mode register prior to loading the corresponding
data bytes into the TxFIFO.
While in this mode, the receiver continuously looks at the received
data stream, whether it is enabled or disabled. If disabled, it sets the
RxRDY status bit and loads the character into the RxFIFO if the
received A/D bit is a one, but discards the received character if the
received A/D bit is a zero. If the receiver is enabled, all received
characters are transferred to the CPU via the RxFIFO. In either case
when the address character is recognized the data bits are loaded
into the data FIFO while the A/D bit is loaded into the status FIFO
position normally used for parity error (SR [5]). Framing error,
overrun error, and break detect operate normally whether or not the
receiver is enabled. When the automatic modes are in operation the
loading of the address character to the FIFO is controlled by the
MR0 (6) bit.
SC28L202
Product data sheet