SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet - Page 6

• Manufacturer Part Number: SC16IS741IPW,128
• Description: IC UART 16TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS-232 or RS-485r

Specifications of SC16IS741IPW,128

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Features: RS-485
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935290736128

NXP Semiconductors
SC16IS741_1
Product data sheet
7.1 Trigger levels
7.2 Hardware flow control
The SC16IS741 provides independently selectable and programmable trigger levels for
both receiver and transmitter interrupt generation. After reset, both transmitter and
receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one
character. The selectable trigger levels are available via the FCR. The programmable
trigger levels are available via the TLR. If TLR bits are cleared then selectable trigger level
in FCR is used. If TLR bits are not cleared then programmable trigger level in TLR is used.
Hardware flow control is comprised of auto CTS and auto RTS (see
and auto RTS can be enabled/disabled independently by programming EFR[7:6].
With auto CTS, CTS must be active before the UART can transmit data.
Auto RTS only activates the RTS output when there is enough room in the FIFO to receive
data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and
resume trigger levels in the TCR determine the levels at which RTS is
activated/deactivated. If TCR bits are cleared then selectable trigger levels in FCR are
used in place of TCR.
If both auto CTS and auto RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus, overrun
errors are eliminated during hardware flow control. If not enabled, overrun errors occur if
the transmit data rate exceeds the receive FIFO servicing latency.
Fig 4.
Autoflow control (auto RTS and auto CTS) example
FIFO
FIFO
RX
TX
UART 1
Single UART with I
SERIAL TO
TO SERIAL
PARALLEL
PARALLEL
CONTROL
CONTROL
Rev. 01 — 29 April 2010
FLOW
FLOW
RTS
CTS
RX
TX
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
TX
CTS
RX
RTS
SERIAL TO
TO SERIAL
PARALLEL
PARALLEL
CONTROL
CONTROL
FLOW
FLOW
UART 2
SC16IS741
Figure
© NXP B.V. 2010. All rights reserved.
FIFO
FIFO
4). Auto CTS
RX
TX
002aab656
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