SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet
SC16IS741IPW,128
Specifications of SC16IS741IPW,128
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SC16IS741IPW,128 Summary of contents
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SC16IS741 Single UART with I and receive FIFOs, IrDA SIR built-in support Rev. 01 — 29 April 2010 1. General description The SC16IS741 is a slave I UART. It offers data rates Mbit/s and guarantees low operating ...
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... NXP Semiconductors Fully programmable character formatting 5-bit, 6-bit, 7-bit or 8-bit character Even, odd parity 1, 1 Line break generation and detection Internal Loopback mode Sleep current less than 30 μA at 3.3 V Industrial and commercial temperature ranges Available in the TSSOP16 package 2 2.2 I C-bus features ...
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... NXP Semiconductors 5. Block diagram Fig 1. Fig 2. SC16IS741_1 Product data sheet Single UART with I SC16IS741 RESET SCL SDA C-BUS A1 IRQ 1 kΩ (3.3 V) 1.5 kΩ (2 I2C/SPI XTAL1 XTAL2 2 Block diagram of SC16IS741 I C-bus interface SC16IS741 RESET SCLK CS SO SPI SI IRQ 1 kΩ (3.3 V) 1.5 kΩ ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning n.c. SCL SDA IRQ I2C a. I Fig 3. 6.2 Pin description Table 2. Symbol V DD CS/A0 SI/A1 SO SCL/SCLK SDA IRQ I2C/SPI SC16IS741_1 Product data sheet Single UART with XTAL2 2 15 XTAL1 3 14 RESET SC16IS741IPW CTS 7 10 RTS ...
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... NXP Semiconductors Table 2. Symbol V SS RTS CTS TX RX RESET XTAL1 XTAL2 [1] See 7. Functional description The UART will perform serial-to-I peripheral devices or modems, and I transmitted by the host. The complete status the SC16IS741 UART can be read at any time during functional operation by the host. ...
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... NXP Semiconductors 7.1 Trigger levels The SC16IS741 provides independently selectable and programmable trigger levels for both receiver and transmitter interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one character. The selectable trigger levels are available via the FCR. The programmable trigger levels are available via the TLR ...
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... NXP Semiconductors 7.2.1 Auto RTS Figure 5 are stored in the TCR or FCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted. The sending device (for example, another UART) may send an additional character after ...
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... NXP Semiconductors 7.3 Software flow control Software flow control is enabled through the enhanced feature register and the Modem Control Register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3:0]. Table 3. EFR[ There are two other enhanced features relating to software flow control: • ...
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... NXP Semiconductors 7.3.2 TX Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level programmed in TCR[3:0] or the selectable trigger level in FCR[7:6] Xon1/Xoff2 character is transmitted when the RX FIFO reaches the RESUME trigger level programmed in TCR[7: FIFO falls below the lower selectable trigger level in FCR[7:6] ...
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... NXP Semiconductors 7.4 Hardware reset, Power-On Reset (POR) and software reset These three reset methods are identical and will reset the internal registers as indicated in Table 4. Table 4 Table 4. Register Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register ...
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... NXP Semiconductors 7.5 Interrupts The SC16IS741 has interrupt generation and prioritization capability. The Interrupt Enable Register (IER) enables each of the interrupts and the IRQ signal in response to an interrupt generation. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0]. ...
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... NXP Semiconductors 7.5.1 Interrupt mode operation In Interrupt mode (if any bit of IER[3: the host is informed of the status of the receiver and transmitter by an interrupt signal, IRQ. Therefore not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Fig 8. ...
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... NXP Semiconductors 7.6 Sleep mode Sleep mode is an enhanced feature of the SC16IS741 UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: • The serial data input line, RX, is idle (see conditions”). • ...
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... NXP Semiconductors XTAL1 XTAL2 Fig 10. Prescaler and baud rate generator block diagram DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and most significant byte of the baud rate divisor. If DLL and DLH are both zero, the UART is effectively disabled baud clock will be generated ...
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... NXP Semiconductors Table 8. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 Fig 11. Crystal oscillator circuit reference SC16IS741_1 Product data sheet Single UART with I Baud rates using a 3.072 MHz crystal Divisor used to generate 16× ...
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... NXP Semiconductors 8. Register descriptions The programming combinations for register selection are shown in Table 9. Register name Read mode RHR/THR IER IIR/FCR LCR MCR LSR MSR SPR TCR TLR TXLVL RXLVL EFCR DLL DLH EFR XON1 XON2 XOFF1 XOFF2 [1] MCR[7] can only be modified when EFR[4] is set. ...
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Table 10. SC16IS741 internal registers Register Register Bit 7 Bit 6 address [1] General register set 0x00 RHR bit 7 bit 6 0x00 THR bit 7 bit 6 0x01 IER CTS RTS interrupt [2] interrupt enable [2] enable 0x02 FCR ...
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Table 10. SC16IS741 internal registers …continued Register Register Bit 7 Bit 6 address [8] Enhanced register set 0x02 EFR Auto CTS Auto RTS 0x04 XON1 bit 7 bit 6 0x05 XON2 bit 7 bit 6 0x06 XOFF1 bit 7 bit ...
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... NXP Semiconductors 8.1 Receive Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX pin. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the Line Control Register ...
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... NXP Semiconductors [1] FIFO reset requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of the XTAL1 clock. 8.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. ...
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... NXP Semiconductors Table 13. LCR[ Table 14. LCR[ Table 15. LCR[ SC16IS741_1 Product data sheet Single UART with I LCR[5] parity selection LCR[4] LCR[3] Parity selection parity 0 1 odd parity 1 1 even parity 0 1 forced parity ‘1’ forced parity ‘0’ LCR[2] stop bit length ...
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... NXP Semiconductors 8.5 Line Status Register (LSR) Table 16 Table 16. Bit When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO (next character to be read). Therefore, errors in a character are identified by reading the LSR and then reading the RHR. ...
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... NXP Semiconductors 8.6 Modem Control Register (MCR) The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 17. Bit [1] MCR[7:5] and MCR[2] can only be modified when EFR[4] is set, that is, EFR[ write enable. SC16IS741_1 Product data sheet ...
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... NXP Semiconductors 8.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the host. It also indicates when a control input from the modem changes state. Table 18. Bit SC16IS741_1 ...
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... NXP Semiconductors 8.8 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, modem status, Xoff received, or CTS/RTS change of state from LOW to HIGH. The IRQ output signal is activated in response to interrupt generation ...
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... NXP Semiconductors 8.9 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 20. Bit 7:6 5:1 0 Table 21. Priority level SC16IS741_1 Product data sheet Single UART with I Table 20 shows Interrupt Identification Register bit settings. ...
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... NXP Semiconductors 8.10 Enhanced Features Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. shows the enhanced feature register bit settings. Table 22. Bit Symbol 7 EFR[7] 6 EFR[6] 5 EFR[5] 4 EFR[4] 3:0 EFR[3:0] 8.11 Division registers (DLL, DLH) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator ...
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... NXP Semiconductors 8.12 Transmission Control Register (TCR) This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. settings. Table 23. Bit 7:4 3:0 TCR trigger levels are available from characters with a granularity of four. Remark: TCR can only be written to when EFR[ and MCR[ The programmer must program the TCR such that TCR[3:0] > ...
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... NXP Semiconductors 8.15 Receiver FIFO Level register (RXLVL) This register is a read-only register, it reports the fill level of the receive FIFO. That is, the number of characters in the RX FIFO. Table 26. Bit 7 6:0 8.16 Extra Features Control Register (EFCR) Table 27. Bit SC16IS741_1 Product data sheet ...
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... NXP Semiconductors 9. RS-485 features 9.1 Auto RS-485 RTS control Normally the RTS pin is controlled by MCR bit hardware flow control is enabled, the logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR register bit 4 will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTS pin ...
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... NXP Semiconductors 9.3.2 Auto address detection If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the address byte) the receiver will try to detect an address byte that matches the programmed character in the XOFF2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the XOFF2 register, the receiver will discard these data ...
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... NXP Semiconductors SDA SCL Fig 13. START and STOP conditions The number of data bytes transferred between the START and STOP condition from transmitter to receiver is not limited. Each byte, which must be eight bits long, is transferred serially with the most significant bit first, and is followed by an acknowledge bit ...
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... NXP Semiconductors There are two exceptions to the ‘acknowledge after every byte’ rule. The first occurs when a master is a receiver: it must signal an end of data to the transmitter by not signalling an acknowledge on the last byte that has been clocked out of the slave. The acknowledge related clock, generated by the master should still take place, but the SDA line will not be pulled down ...
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... NXP Semiconductors Another way for a master to communicate with several different devices would be by using a ‘repeated START’. After the last byte of the transaction was transferred, including its acknowledge (or negative acknowledge), the master issues another START, followed by address byte and data—without effecting a STOP. The master may communicate with a number of different devices, combining ‘ ...
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... NXP Semiconductors 10.3 Addressing Before any data is transmitted or received, the master must send the address of the receiver via the SDA line. The first byte after the START condition carries the address of the slave device and the read/write bit. be selected by using A1 and A0 pins. For example, if these 2 pins are connected to V then the SC16IS741’ ...
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... NXP Semiconductors Table 29 SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the UART internal registers. Bit 7 is not used with the I SPI interface to indicate a read or a write operation. S SLAVE ADDRESS White block: host to SC16IS741 ...
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SCLK CH1 CH0 X SI R/W R A[3:0] = register address; CH1 = 0, CH0 = 0 a. Register write SCLK CH1 CH0 X R ...
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... NXP Semiconductors Table 30. Bit 7 6:3 2:1 0 12. Limiting values Table 31. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol tot P/out T amb stg [1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present. ...
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... NXP Semiconductors Table 32. Static characteristics ± − ° 2 amb Symbol Parameter Outputs TX, RTS HIGH-level output voltage OH V LOW-level output voltage OL C output capacitance o Output IRQ V LOW-level output voltage OL C output capacitance C-bus input/output SDA V HIGH-level input voltage IH V LOW-level input voltage ...
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... NXP Semiconductors 14. Dynamic characteristics 2 Table 33. I C-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; ± − ° 2 amb an input voltage All output load = 25 pF, except SDA output load = 400 pF. ...
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... NXP Semiconductors Fig 21. SCL delay after reset protocol SCL SDA Fig 22. I Fig 23. I Fig 24. I SC16IS741_1 Product data sheet Single UART with I RESET t w(rst) SCL START bit 7 bit 6 condition MSB (A6) (S) (A7 SU;STA LOW HIGH BUF SU;DAT HD;STA Rise and fall times refer to V ...
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... NXP Semiconductors SLAVE ADDRESS SDA IRQ MODEM pin Fig 25. Modem input pin interrupt RX IRQ Fig 26. Receive interrupt SLAVE ADDRESS SDA IRQ Fig 27. Receive interrupt clear SLAVE ADDRESS SDA IRQ Fig 28. Transmit interrupt clear SC16IS741_1 Product data sheet Single UART with MSR REGISTER ...
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... NXP Semiconductors Table 34. f dynamic characteristics XTAL ± − ° 2 amb Symbol Parameter t pulse width HIGH WH t pulse width LOW WL f frequency on pin XTAL XTAL [1] Applies to external clock, crystal oscillator max. 24 MHz. 1 -------------- - f = [2] XTAL clk external clock Fig 29. External clock timing ...
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... NXP Semiconductors Table 35. SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; ± − ° 2 amb an input voltage All output load = 25 pF, unless otherwise specified Symbol Parameter t CS HIGH to SO 3-state delay time ...
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... NXP Semiconductors CS SCLK R/W SO IRQ R A[3:0] = THR (0x00); CH1 = 0; CH0 = 0 Fig 31. SPI write THR to clear TX INT CS SCLK R/W SO IRQ R A[3:0] = RHR (0x00); CH1 = 0; CH0 = 0 Fig 32. Read RHR to clear RX INT SC16IS741_1 Product data sheet Single UART with CH1 CH0 CH1 CH0 X D7 ...
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... NXP Semiconductors 15. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 34. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 18. Abbreviations Table 38. Acronym CPU FIFO 2 I C-bus IrDA LCD MIR POR SIR SPI UART 19. Revision history Table 39 ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2.2 I C-bus features . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Trigger levels . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 Hardware flow control . . . . . . . . . . . . . . . . . . . . 6 7 ...