SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet - Page 40

• Manufacturer Part Number: SC16IS741IPW,128
• Description: IC UART 16TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS-232 or RS-485r

Specifications of SC16IS741IPW,128

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Features: RS-485
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935290736128

NXP Semiconductors
14. Dynamic characteristics
Table 33.
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
V
an input voltage of V
[1]
[2]
[3]
[4]
SC16IS741_1
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
d(int_v)modem
d(int_clr)modem
d(int_v)rx
d(int_clr)rx
d(int_clr)tx
d(rst-SCL)
d(SCL-A)
d(SDA-A)
d(A-SCL)
d(A-SDA)
w(rst)
DD
= 2.5 V
A detailed description of the I
manual”. This may be found at www.nxp.com/acrobat_download/usermanuals/UM10204.pdf.
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a
minimum of 25 ms.
2 XTAL1 clocks or 3 μs, whichever is less.
The device will not acknowledge if an I
I
±
2
C-bus timing specifications
0.2 V, T
Parameter
SCL clock frequency
bus free time between a STOP and START
condition
hold time (repeated) START condition
set-up time for a repeated START condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
modem interrupt valid delay time
modem interrupt clear delay time
receive interrupt valid delay time
receive interrupt clear delay time
transmit interrupt clear delay time
SCL delay time after reset
delay time from SCL to address
delay time from SDA to address
delay time from address to SCL
delay time from address to SDA
reset pulse width
SS
amb
to V
=
DD
−
40
. All output load = 25 pF, except SDA output load = 400 pF.
2
C-bus specification, with applications, is given in user manual UM10204: “I
°
C to +85
2
C-bus transaction occurs during the ‘SCL delay time after reset’.
°
[1]
C; or V
Single UART with I
DD
Rev. 01 — 29 April 2010
= 3.3 V
Conditions
SCL LOW to
data out valid
±
0.3 V, T
2
amb
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
=
[3][4]
−
40
[2]
°
C to +95
Standard mode
Min
250
4.7
4.0
4.7
4.7
4.7
4.0
0.2
0.2
0.2
1.0
0.2
0
0
3
3
-
-
-
-
-
-
-
-
-
I
2
C-bus
°
C; and refer to V
1000
Max
100
300
0.6
0.6
50
30
30
30
30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
C-bus specification and user
SC16IS741
Min
150
1.3
0.6
0.6
0.6
1.3
0.6
0.2
0.2
0.2
0.2
0.5
Fast mode
0
0
3
3
© NXP B.V. 2010. All rights reserved.
-
-
-
-
-
-
-
-
-
I
2
C-bus
IL
and V
Max
400
300
300
0.6
0.6
50
30
30
30
30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IH
40 of 52
Unit
kHz
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
ns
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
μs
with