SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet - Page 31

• Manufacturer Part Number: SC16IS741IPW,128
• Description: IC UART 16TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS-232 or RS-485r

Specifications of SC16IS741IPW,128

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Features: RS-485
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935290736128

NXP Semiconductors
10. I
SC16IS741_1
Product data sheet
2
C-bus operation
9.3.2 Auto address detection
10.1 Data transfers
If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the
address byte) the receiver will try to detect an address byte that matches the programmed
character in the XOFF2 register. If the received byte is a data byte or an address byte that
does not match the programmed character in the XOFF2 register, the receiver will discard
these data. Upon receiving an address byte that matches the Xoff2 character, the receiver
will be automatically enabled if not already enabled, and the address character is pushed
into the RX FIFO along with the parity bit (in place of the parity error bit). The receiver also
generates a line status interrupt (IER[2] must be set to ‘1’ at this time). The receiver will
then receive the subsequent data from the ‘master’ station until being disabled by the
controller after having received a message from the ‘master’ station.
If another address byte is received and this address byte does not match Xoff2 character,
the receiver will be automatically disabled and the address byte is ignored. If the address
byte matches Xoff2 character, the receiver will put this byte in the RX FIFO along with the
parity bit in the parity error bit (LSR bit 2).
The two lines of the I
lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the
bus is not busy. Each device is recognized by a unique address whether it is a
microcomputer, LCD driver, memory or keyboard interface and can operate as either a
transmitter or receiver, depending on the function of the device. A device generating a
message or data is a transmitter, and a device receiving the message or data is a
receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a
microcontroller or a memory can both transmit and receive data.
One data bit is transferred during each clock pulse (see
line must remain stable during the HIGH period of the clock pulse in order to be valid.
Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW
transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START
condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP
condition (see
and free again at a certain time interval after the STOP condition. The START and STOP
conditions are always generated by the master.
Fig 12. Bit transfer on the I
Figure
SDA
SCL
2
Single UART with I
C-bus are a serial data line (SDA) and a serial clock line (SCL). Both
13). The bus is considered to be busy after the START condition
Rev. 01 — 29 April 2010
2
C-bus
data valid
data line
stable;
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
allowed
change
of data
Figure
12). The data on the SDA
SC16IS741
mba607
© NXP B.V. 2010. All rights reserved.
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