SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet - Page 32

• Manufacturer Part Number: SC16IS741IPW,128
• Description: IC UART 16TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS-232 or RS-485r

Specifications of SC16IS741IPW,128

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Features: RS-485
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935290736128

NXP Semiconductors
SC16IS741_1
Product data sheet
Fig 14. Data transfer on the I
Fig 15. Acknowledge on the I
SDA
SCL
condition
SCL from master
START
by transmitter
S
data output
data output
by receiver
MSB
The number of data bytes transferred between the START and STOP condition from
transmitter to receiver is not limited. Each byte, which must be eight bits long, is
transferred serially with the most significant bit first, and is followed by an acknowledge bit
(see
master. The device that acknowledges has to pull down the SDA line during the
acknowledge clock pulse, while the transmitting device releases this pulse (see
Figure
A slave receiver must generate an acknowledge after the reception of each byte, and a
master must generate one after the reception of each byte clocked out of the slave
transmitter.
0
Fig 13. START and STOP conditions
condition
Figure
START
SDA
SCL
15).
S
2
1
2
C-bus
C-bus
14). The clock pulse related to the acknowledge bit is generated by the
START condition
interrupt within receiver
0
6
S
byte complete,
Single UART with I
Rev. 01 — 29 April 2010
1
7
ACK
8
acknowledgement signal
from receiver
6
7
2
0
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
clock line held LOW
while interrupt is serviced
8
1
002aab013
2 to 7
transmitter stays off of the bus
during the acknowledge clock
acknowledgement signal
from receiver
ACK
8
STOP condition
SC16IS741
P
© NXP B.V. 2010. All rights reserved.
mba608
condition
STOP
P
002aab012
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