SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet - Page 18

• Manufacturer Part Number: SC16IS741IPW,128
• Description: IC UART 16TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS-232 or RS-485r

Specifications of SC16IS741IPW,128

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Features: RS-485
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935290736128

Table 10.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Register
address
Enhanced register set
0x02
0x04
0x05
0x06
0x07
These registers are accessible only when LCR[7] = 0.
These bits in can only be modified if register bit EFR[4] is enabled.
These bits are reserved and should be set to 0.
After Receive FIFO or Transmit FIFO reset (through FCR[1:0]), the user must wait at least 2 × T
Burst reads on the serial interface (that is, reading multiple elements on the I
without de-asserting the CS pin), should not be performed on the IIR register.
These registers are accessible only when MCR[2] = 1 and EFR[4] = 1.
The special register set is accessible only when LCR[7] = 1 and not 0xBF.
Enhanced Feature Registers are only accessible when LCR = 0xBF.
SC16IS741 internal registers
Register
EFR
XON1
XON2
XOFF1
XOFF2
[8]
Bit 7
Auto CTS
bit 7
bit 7
bit 7
bit 7
Bit 6
Auto RTS
bit 6
bit 6
bit 6
bit 6
…continued
Bit 5
special
character
detect
bit 5
bit 5
bit 5
bit 5
Bit 4
enable
enhanced
functions
bit 4
bit 4
bit 4
bit 4
2
C-bus without a STOP or repeated START condition, or reading multiple elements on the SPI bus
Bit 3
software flow
control bit 3
bit 3
bit 3
bit 3
bit 3
clk
of XTAL1 before reading or writing data to RHR and THR, respectively.
Bit 2
software flow
control bit 2
bit 2
bit 2
bit 2
bit 2
bit 1
bit 1
Bit 1
software flow
control bit 1
bit 1
bit 1
Bit 0
software flow
control bit 0
bit 0
bit 0
bit 0
bit 0
R/W
R/W
R/W
R/W
R/W
R/W