SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet - Page 11

• Manufacturer Part Number: SC16IS741IPW,128
• Description: IC UART 16TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS-232 or RS-485r

Specifications of SC16IS741IPW,128

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Features: RS-485
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935290736128

NXP Semiconductors
SC16IS741_1
Product data sheet
7.5 Interrupts
The SC16IS741 has interrupt generation and prioritization capability. The Interrupt Enable
Register (IER) enables each of the interrupts and the IRQ signal in response to an
interrupt generation. When an interrupt is generated, the IIR indicates that an interrupt is
pending and provides the type of interrupt through IIR[5:0].
interrupt control functions.
Table 6.
It is important to note that for the framing error, parity error, and break conditions, LSR[7]
generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,
and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always
represent the error status for the received character at the top of the RX FIFO. Reading
the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of
the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the IIR.
IIR[5:0]
00 0001
00 0110
00 1100
00 0100
00 0010
00 0000
01 0000
10 0000
Priority
level
none
1
2
2
3
4
6
7
Summary of interrupt control functions
none
CTS, RTS
Interrupt type
receiver line status
RX time-out
RHR interrupt
THR interrupt
Modem status
Xoff interrupt
Single UART with I
Rev. 01 — 29 April 2010
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Interrupt source
none
OE, FE, PE, or BI errors occur in characters in the
RX FIFO
Stale data in RX FIFO
Receive data ready (FIFO disable) or
RX FIFO above trigger level (FIFO enable)
Transmit FIFO empty (FIFO disable) or
TX FIFO passes above trigger level (FIFO enable)
Change of state of modem input pins
Receive Xoff character(s)/ special character
RTS pin or CTS pin change state from active (LOW)
to inactive (HIGH)
Table 6
SC16IS741
summarizes the
© NXP B.V. 2010. All rights reserved.
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