PEF 20550 H V2.1 Infineon Technologies, PEF 20550 H V2.1 Datasheet - Page 194

• Manufacturer Part Number: PEF 20550 H V2.1
• Description: IC INTERFACE CTRLR PCM MQFP80
• Manufacturer: Infineon Technologies
• Series: ELIC®r

Specifications of PEF 20550 H V2.1

• Function: Line Card Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-SQFP
• Includes: Change Detection, Power-Up Reset Generation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF20550HV2.1XT; PEF20550HV21XP; SP000007794; SP000007795

of digital data are transmitted on the SLD bus from the ELIC to the slave (downstream
direction). During the second half of the frame when FSC is low, four bytes of data are
transferred from the slave back to the ELIC (upstream direction).
Channel B1 and B2 are 64 kBit/s channels reserved for voice and data to be routed to
and from the PCM highways. The third and seventh byte are used to transmit and
receive control information for programming the slave devices (feature control channel).
The last byte in each direction is reserved for signaling data.
SLD (Subscriber Line Data) Interface
The SLD bus is used by the ELIC to interface with the subscriber line devices. A Serial
Interface Port (SIP) is used for the transfer of all digital voice and data, feature control
and signaling information between the individual subscriber line devices, the PCM
highways and the control backplane. The SLD approach provides a common interface
for one analog or digital component per line. The ELIC switches the PCM data
transparently switched onto the PCM highways.
There are three wires connecting each subscriber line device and the ELIC: two common
clock signals shared among all devices, and a unique bidirectional data wire for each of
the eight SIP ports. The direction signal (FSC) is an 8 kHz clock output from the ELIC
(master) that serves as a frame synch to the subscriber line devices (slave) as well as a
transfer indicator. The data is transferred at a 512 kHz data rate, clocked by the
subscriber clock (DCL). When FSC is high (first half of the 125 s SLD frame), four bytes
Figure 59
SLD Frame Structure
Semiconductor Group
SIP
FSC
(8 kHz)
DCL
(512 kHz)
(512 kbit/s)
B1 : 64 kbit/s Channel
B2 : 64 kbit/s Channel
FC : Feature Control Channel (8 Bit)
SIG : Signaling Channel (8 Bit)
TS 0
B1
TS 1
B2
Downstream
SIP Output
TS 2
FC
194
TS 3
SIG
TS 4
B1
TS 5
B2
Upstream
SIP Input
TS 6
Application Hints
FC
PEB 20550
PEF 20550
TS 7
SIG
ITD08038
01.96