PEF 20550 H V2.1 Infineon Technologies, PEF 20550 H V2.1 Datasheet - Page 100
PEF 20550 H V2.1
Manufacturer Part Number
PEF 20550 H V2.1
Description
IC INTERFACE CTRLR PCM MQFP80
Manufacturer
Infineon Technologies
Series
ELIC®r
Datasheet
1.PEF_20550_H_V2.1.pdf
(407 pages)
Specifications of PEF 20550 H V2.1
Function
Line Card Controller
Interface
ISDN, PCM
Number Of Circuits
1
Voltage - Supply
5V
Current - Supply
15mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-SQFP
Includes
Change Detection, Power-Up Reset Generation
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Other names
PEF20550HV2.1XT
PEF20550HV21XP
SP000007794
SP000007795
PEF20550HV21XP
SP000007794
SP000007795
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(CMDR:XME) must also be set. If transparent or direct data is sent, CMDR:XME may but
need not be set. If CMDR:XME is not set, the SACCO will repeatedly request for the next
data block by means of a XPR-interrupt as soon as the CPU accessible part of the
XFIFO is available. This process will be repeated until the CPU indicates the end of
message per command, after which frame transmission is ended by appending the CRC
and closing flag sequence.
If no more data is available in the XFIFO prior to the arrival of XME, the transmission of
the frame is terminated with an abort sequence and the CPU is notified per interrupt
(EXIR:XDU). The frame may also be aborted per software (CMDR:XRES).
Figure 49 outlines the data transmission sequence from the CPU’s point of view:
Figure 49
Interrupt Driven Transmission Sequence (flow diagram)
Semiconductor Group
Command
XTF or XDD
N
N
(up to 32 Bytes)
Write Data
to XFIFO
XTF/XPD or XDD
Command XME+
Pool Ready
Massage
Transmit
START
End of
END
?
?
Y
Y
100
ITD05847
XPR Interrupt or Set
XFW Bit in STAR Register
Operational Description
PEB 20550
PEF 20550
01.96
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