PEF 20550 H V2.1 Infineon Technologies, PEF 20550 H V2.1 Datasheet - Page 117
PEF 20550 H V2.1
Manufacturer Part Number
PEF 20550 H V2.1
Description
IC INTERFACE CTRLR PCM MQFP80
Manufacturer
Infineon Technologies
Series
ELIC®r
Datasheet
1.PEF_20550_H_V2.1.pdf
(407 pages)
Specifications of PEF 20550 H V2.1
Function
Line Card Controller
Interface
ISDN, PCM
Number Of Circuits
1
Voltage - Supply
5V
Current - Supply
15mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-SQFP
Includes
Change Detection, Power-Up Reset Generation
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Other names
PEF20550HV2.1XT
PEF20550HV21XP
SP000007794
SP000007795
PEF20550HV21XP
SP000007794
SP000007795
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Write
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3.8.6.5 SACCO-B Initialization Example
Configure the SACCO-B as secondary station for an upstream (non-PBC) group
controller
Write
Write
Write
Write
Write
Write
Reset the SACCO-B’s FIFOs
Write
Read
Read
3.8.6.4 PCM- and CFI-Interface Activation Example
Write
Enable upstream PCM-port 0, time slot 5
Write
Write
Semiconductor Group
OMDR = EE
MADR = 0F
MAAR = 89
MACR = 60
STAR
MODE = 48
RAH1 = 00
RAH2 = 00
RAL1 = 89
RAL2 = FF
CCR2 = 08
CCR1 = 98
CMDR = C1
ISTA = 08
ISTA_B = 10
H
H
H
H
H
H
H
H
H
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H
H
see chapter 3.8.5.
set all bits of time slot to low impedance
PCM-port 0, time slot 5
write only single tristate control position
Wait for STAR:MAC = 0
set SACCO-B to 8-bit non-auto mode; switch receiver active
the high-byte comparison registers should be set to 00
when using non-auto mode
8-bit address of SACCO-B
8-bit group address (broadcast by group controller)
TxDB pin enabled; standard data sampling; RFS-interrupt
disabled
power-up SACCO-B in point-to-point configuration and
clock mode 0 with single rate clock;
inter frame timefill = flags;
TxDB is push-pull output
reset CPU accessible and CPU inaccessible part of RFIFO,
and reset XFIFO; the interrupt line will go active
interrupt of SACCO-B
transmit pool ready
117
Operational Description
PEB 20550
PEF 20550
01.96
H
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