PEF 20550 H V2.1 Infineon Technologies, PEF 20550 H V2.1 Datasheet - Page 136

• Manufacturer Part Number: PEF 20550 H V2.1
• Description: IC INTERFACE CTRLR PCM MQFP80
• Manufacturer: Infineon Technologies
• Series: ELIC®r

Specifications of PEF 20550 H V2.1

• Function: Line Card Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-SQFP
• Includes: Change Detection, Power-Up Reset Generation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF20550HV2.1XT; PEF20550HV21XP; SP000007794; SP000007795

CSS
CSM
4.6.7
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Note: If CSS = 0 is selected, CSM and PMOD:PSM must be programmed identical.
CSP1..0
Semiconductor Group
bit 7
CSS
Configurable Interface Mode Register 1 (CMD1)
Clock Source Selection.
0…PDC and PFS are used as clock and framing source for the CFI. Clock
1…DCL and FSC are selected as clock and framing source for the CFI.
If EMOD:ECMD2 is set to ’0’, then CSS has to be set to ’0’ (see chapter 4.5).
CFI-Synchronization Mode.
The rising FSC-edge synchronizes the CFI-frame.
0…FSC is evaluated with every falling edge of DCL.
1…FSC is evaluated with every rising edge of DCL.
Clock Source Prescaler 1,0.
The clock source frequency is divided according to the following table to
obtain the CFI-reference clock CRCL.
CSP1,0
00
01
10
11
CSM
and framing signals derived from these sources are output on DCL and
FSC.
H
CSP1
CSP0
136
CMD1
Prescaler Divisor
2
1.5
1
not allowed
read/write
read/write
Detailed Register Description
CMD0
address: 16
address: 2C
CIS1
PEB 20550
PEF 20550
bit 0
H
H
CIS0
01.96