LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet - Page 69

• Manufacturer Part Number: LPC4350FET256,551
• Description: IC MCU 32BIT 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC43xxr

Specifications of LPC4350FET256,551

• Core Processor: ARM® Cortex™-M4/M0
• Core Size: 32-Bit Dual-Core
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 146
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 264K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 4.
[1]
Table 5.
[1]
LPC4350_30_20_10
Objective data sheet
Boot mode BOOT_SRC
USB1
SPI (SSP)
USART3
Boot mode
UART
SPIFI
EMC 8-bit
EMC 16-bit
EMC 32-bit
USB0
USB1
SPI (SSP)
USART3
The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Boot mode when OTP BOOT_SRC bits are programmed
Boot mode when OPT BOOT_SRC bits are zero
bit 3
0
1
1
7.13 Memory mapping
The memory map shown in
the Cortex-M0 processors and all SRAM is shared between both processors. Each
processor uses its own ARM private bus memory map for the NVIC and other system
functions.
Pins
P2_9
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
BOOT_SRC
bit 2
1
0
0
P2_8
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
All information provided in this document is subject to legal disclaimers.
BOOT_SRC
bit 1
1
0
0
Rev. 2.1 — 23 September 2011
P1_2
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
Figure 9
BOOT_SRC
bit 0
1
0
1
P1_1
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
and
Figure 10
Description
Boot from device connected to USART0 using pins
P2_0 and P2_1.
Boot from Quad SPI flash connected to the SPIFI
interface on P3_3 to P3_8
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
Boot from USB0
Boot from USB1.
Boot from SPI flash connected to the SSP0
interface on P3_3, P3_6, P3_7 and P3_8
Boot from device connected to USART3 using pins
P2_3 and P2_4.
Description
Boot from USB1.
Boot from SPI flash connected to the SSP0
interface on P3_3, P3_6, P3_7 and P3_8
Boot from device connected to USART3 using pins
P2_3 and P2_4.
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
is global to both the Cortex-M4 and
[1]
.
© NXP B.V. 2011. All rights reserved.
[1]
[1]
.
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