LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet - Page 68

• Manufacturer Part Number: LPC4350FET256,551
• Description: IC MCU 32BIT 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC43xxr

Specifications of LPC4350FET256,551

• Core Processor: ARM® Cortex™-M4/M0
• Core Size: 32-Bit Dual-Core
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 146
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 264K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 4.
LPC4350_30_20_10
Objective data sheet
Boot mode BOOT_SRC
Pin state
UART
SPIFI
EMC 8-bit
EMC 16-bit
EMC 32-bit
USB0
Boot mode when OTP BOOT_SRC bits are programmed
bit 3
0
0
0
0
0
0
0
7.12 Boot ROM
7.11 In-System Programming (ISP)
In-System programming (ISP) is programming or reprogramming the on-chip SRAM
memory, using the boot loader software and the USART0 serial port. This can be done
when the part resides in the end-user board. ISP allows to load data into on-chip SRAM
and execute code from on-chip SRAM.
The internal ROM memory is used to store the boot code of the LPC4350/30/20/10. After
a reset, the ARM processor will start its code execution from this memory.
The boot ROM memory includes the following features:
AES capable parts also support:
Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If
the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is
determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1.
•
•
•
•
•
•
•
•
BOOT_SRC
bit 2
0
0
0
0
1
1
1
ROM memory size is 64 kB.
Supports booting from UART interfaces and external static memory such as NOR
flash, SPI flash, quad SPI flash.
Includes APIs for power control and OTP programming.
Includes SPIFI drivers.
Includes a flexible USB device stack that supports Human Interface Device (HID),
Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.
CMAC authentication on the boot image.
Secure booting from an encrypted image. In development mode booting from a plain
text image is possible. Development mode is terminated by programming the AES
key.
API for AES programming.
All information provided in this document is subject to legal disclaimers.
BOOT_SRC
bit 1
0
0
1
1
0
0
1
Rev. 2.1 — 23 September 2011
BOOT_SRC
bit 0
0
1
0
1
0
1
0
Description
Boot source is defined by the reset state of P1_1,
P1_2, P2_8 pins, and P2_9. See
Boot from device connected to USART0 using pins
P2_0 and P2_1.
Boot from Quad SPI flash connected to the SPIFI
interface using pins P3_3 to P3_8.
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
Boot from USB0.
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
© NXP B.V. 2011. All rights reserved.
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