LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet - Page 60

• Manufacturer Part Number: LPC4350FET256,551
• Description: IC MCU 32BIT 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC43xxr

Specifications of LPC4350FET256,551

• Core Processor: ARM® Cortex™-M4/M0
• Core Size: 32-Bit Dual-Core
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 146
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 264K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 3.
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See
LPC4350_30_20_10
Objective data sheet
Symbol
CLK1
CLK2
CLK3
Debug pins
DBGEN
TCK/SWDCLK
TRST
TMS/SWDIO
TDO/SWO
Pin description
T10
D14
P12
L4
J5
M4
K6
K5
x
x
x
x
x
x
x
x
…continued
-
K6
-
A6
H2
B4
C4
H3
-
141 99
-
41
38
42
44
46
-
-
28
27
29
30
31
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
-
68
-
18
17
19
20
21
[5]
[5]
[5]
[3]
[3]
[3]
[3]
[3]
O;
PU
O;
PU
O;
PU
I; PD I
I; F
I; PU I
I; PU I
O;
PU
O
O
-
-
-
O
-
O
O
O
-
-
I/O SD_CLK — SD/MMC card clock.
O
O
I/O I2S1_RX_SCK — Receive Clock. It is driven by the
O
O
-
-
-
O
-
I/O I2S1_RX_SCK — Receive Clock. It is driven by the
I
O
Description
EMC_CLK1 — SDRAM clock 1.
CLKOUT — Clock output pin.
R — Function reserved.
R — Function reserved.
R — Function reserved.
CGU_OUT0 — CGU spare clock output 0.
R — Function reserved.
I2S1_TX_MCLK — I2S1 transmit master clock.
EMC_CLK3 — SDRAM clock 3.
CLKOUT — Clock output pin.
R — Function reserved.
R — Function reserved.
EMC_CLK23 — SDRAM clock 2 and clock 3
combined.
I2S0_TX_MCLK — I2S transmit master clock.
master and received by the slave. Corresponds to the
signal SCK in the I
EMC_CLK2 — SDRAM clock 2.
CLKOUT — Clock output pin.
R — Function reserved.
R — Function reserved.
R — Function reserved.
CGU_OUT1 — CGU spare clock output 1.
R — Function reserved.
master and received by the slave. Corresponds to the
signal SCK in the I
JTAG interface control signal. Also used for boundary
scan.
Test Clock for JTAG interface (default) or Serial Wire
(SW) clock.
Test Reset for JTAG interface.
Test Mode Select for JTAG interface (default) or SW
debug data input/output.
Test Data Out for JTAG interface (default) or SW trace
output.
32-bit ARM Cortex-M4/M0 microcontroller
Table
LPC4350/30/20/10
2.
2
2
S-bus specification.
S-bus specification.
© NXP B.V. 2011. All rights reserved.
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